Memory device, electronic device and operating method of memory device

Abstract

A memory device, an electronic device, and a method of operating the memory device are provided. The memory device includes: a volatile memory including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, and configured to provide output data stored in target memory cells, among the plurality of memory cells, based on a first read command and an address received from a host; a recovery logic circuit configured to provide hint data indicating first bit lines to which defective cells are connected, and second bit lines to which normal cells are connected, among the plurality of bit lines; and an Error Correction Circuit (ECC) configured to generate corrected data by correcting an error in the output data based on the output data and the hint data, and to provide the corrected data to the host.

What is claimed is: 
     
       1. A memory device comprising:
 a volatile memory comprising a plurality of memory cells, a plurality of word lines and a plurality of bit lines, and configured to provide output data stored in target memory cells, among the plurality of memory cells, based on a first read command and an address received from a host; 
 a recovery logic circuit configured to provide hint data indicating first bit lines to which defective cells are connected, and second bit lines to which other cells are connected, among the plurality of bit lines; 
 an Error Correction Circuit (ECC) configured to generate corrected data by correcting an error in the output data based on the output data and the hint data, and to provide the corrected data to the host; and 
 a recovery controller configured to control the volatile memory to store first test pattern data in the target memory cells, control the volatile memory to read first test data from the target memory cells, control the volatile memory to store second test pattern data in the target memory cells, control the volatile memory to read second test data from the target memory cells, and generate the hint data based on the first test data and the second test data. 
 
     
     
       2. The memory device of  claim 1 , wherein the recovery logic circuit comprises:
 a hint data buffer configured to temporarily store the hint data; and 
 a test data buffer configured to temporarily store test data. 
 
     
     
       3. The memory device of  claim 2 , wherein the recovery controller is further configured to:
 transfer a first write command, the first test pattern data, and the address to the volatile memory; 
 transfer a second read command and the address to the volatile memory; 
 store the first test data output from the volatile memory in the test data buffer; 
 transfer a second write command, the second test pattern data, and the address to the volatile memory; 
 transfer a third read command and the address to the volatile memory; and 
 store the second test data output from the volatile memory in the test data buffer. 
 
     
     
       4. The memory device of  claim 3 , wherein the recovery controller is further configured to:
 perform an XOR operation on the first test data and the second test data; and 
 store first result data, at least one bit of the first result data having a first value, according to a result of the XOR operation as the hint data in the hint data buffer. 
 
     
     
       5. The memory device of  claim 4 , wherein the recovery controller is further configured to:
 transmit a setting request signal to change any one or any combination of an internal voltage and a clock frequency for operating the volatile memory to the host based on all values of second result data generated by the XOR operation being a second value different from the first value; and 
 control the volatile memory to perform a write operation based on the first test pattern data, a read operation based on the first test data, a write operation based on the second test pattern data, and a read operation based on the second test data, based on any one or any combination of the internal voltage and the clock frequency being changed according to the setting request signal. 
 
     
     
       6. The memory device of  claim 5 , wherein the recovery controller is further configured to request the host to generate a reduced internal voltage having a level lower than the internal voltage based on all values of the second result data being the second value. 
     
     
       7. The memory device of  claim 5 , wherein the recovery controller is further configured to request the host to generate a clock having an increased clock frequency, greater than the clock frequency, based on all values of the second result data being the second value. 
     
     
       8. The memory device of  claim 2 , wherein the recovery controller is further configured to:
 back up output data to the test data buffer and control the volatile memory to store test pattern data in the target memory cells; and 
 control the volatile memory to store the backed-up output data in the target memory cells after the hint data is generated. 
 
     
     
       9. The memory device of  claim 1 , wherein the ECC is further configured to:
 generate a parity bit with respect to data received from the host; 
 correct the output data using the hint data; 
 transmit the corrected data to the host; 
 output data in which at least one error bit is corrected by performing an XOR operation on the output data and the hint data; 
 generate syndrome data based on the data in which the at least one error bit is corrected; 
 calculate coefficients of an error location equation based on a reciprocal of a position of an error bit based on the syndrome data; 
 calculate a position of the error bit in the data in which the at least one error bit is corrected by using the syndrome data and the coefficients of the error location equation; 
 correct the error by inverting a value of the error bit; and 
 output the corrected data. 
 
     
     
       10. An electronic device comprising:
 an application processor configured to output a first read command and an address; 
 a buffer comprising a plurality of volatile memories, a multiplexer configured to select a volatile memory corresponding to the address from among the plurality of volatile memories, and an Error Correction Circuit (ECC) configured to correct an error occurring in output data read from the volatile memory through a read operation performed according to the first read command; and 
 a recovery logic circuit configured to provide hint data indicating first bit lines to which bad cells are respectively connected and second bit lines to which other cells are connected, 
 wherein the ECC is further configured to correct the error based on first hint data corresponding to the selected volatile memory and the output data, and provide corrected data to the application processor, and 
 wherein the recovery logic circuit comprises a recovery controller configured to control the selected volatile memory to store first test pattern data, control the selected volatile memory to read first test data, control the selected volatile memory to store second test pattern data, control the selected volatile memory to read second test data, and generate the hint data based on the first test data and the second test data provided from the selected volatile memory. 
 
     
     
       11. The electronic device of  claim 10 , wherein the recovery logic circuit comprises:
 a hint data buffer configured to temporarily store the first hint data; and 
 a test data buffer configured to temporarily store test data. 
 
     
     
       12. The electronic device of  claim 11 , wherein the recovery controller is further configured to:
 transfer a first write command, the first test pattern data, and the address to the selected volatile memory; 
 transfer a second read command and the address to the selected volatile memory; 
 store the first test data output from the selected volatile memory in the test data buffer; 
 transfer a second write command, the second test pattern data, and the address to the selected volatile memory; 
 transfer a third read command and the address to the selected volatile memory; and 
 store the second test data output from the selected volatile memory in the test data buffer. 
 
     
     
       13. The electronic device of  claim 12 , wherein the recovery controller is further configured to:
 perform an XOR operation on the first test data and the second test data; and 
 store first result data having at least one first value according to a result of the XOR operation as the hint data in the hint data buffer. 
 
     
     
       14. The electronic device of  claim 13 , further comprising a power supply configured to provide an internal voltage,
 wherein the application processor is further configured to control the power supply, based on a setting request signal, to reduce a level of the internal voltage, and 
 wherein the recovery controller is further configured to:
 transmit the setting request signal to the application processor based on all values of second result data generated by the XOR operation being a second value different from the at least one first value; and 
 control the selected volatile memory to perform a write operation based on the first test pattern data, a read operation based on the first test data, a write operation based on the second test pattern data, and a read operation based on the second test data, based on the level of the internal voltage being changed. 
 
 
     
     
       15. The electronic device of  claim 13 , further comprising a clock generator configured to provide a clock,
 wherein the application processor is further configured to control the clock generator, based on a setting request signal, to increase a clock frequency of the clock, and 
 wherein the recovery controller is further configured to:
 transmit the setting request signal to the application processor based on all values of second result data generated by the XOR operation being a second value different from the at least one first value; and 
 control the selected volatile memory to perform a write operation based on the first test pattern data, a read operation based on the first test data, a write operation based on the second test pattern data, and a read operation based on the second test data, based on the clock frequency being changed. 
 
 
     
     
       16. The electronic device of  claim 11 , wherein the recovery controller is further configured to:
 control the selected volatile memory to store test pattern data after backing up output data to the test data buffer; and 
 control the selected volatile memory to store the output data stored in the test data buffer in target memory cells after the hint data is generated. 
 
     
     
       17. The electronic device of  claim 10 , wherein the ECC is further configured to:
 generate a parity bit with respect to data received from the application processor; 
 correct the output data using the first hint data; 
 transmit the corrected data to the application processor; 
 output data in which at least one error bit is corrected by performing an XOR operation on the output data and the first hint data; 
 generate syndrome data based on the data in which the at least one error bit is corrected; 
 calculate coefficients of an error location equation based on a reciprocal of a position of an error bit based on the syndrome data; 
 calculate a position of the error bit in the data in which the at least one error bit is corrected by using the syndrome data and the coefficients of the error location equation; 
 correct the error by inverting a value of the error bit based on the position; and 
 output the corrected data. 
 
     
     
       18. A method of operating a memory device including a plurality of volatile memories, the method comprising:
 storing first test pattern data in a volatile memory among the plurality of volatile memories; 
 control the volatile memory to read first test data from the volatile memory; 
 control the volatile memory to store second test pattern data in the volatile memory; 
 control the volatile memory to read second test data from the volatile memory; 
 generate hint data based on the first test data and the second test data; 
 receiving a read command and an address indicating the volatile memory from a host; 
 reading data stored in the volatile memory; 
 detecting a 2-bit error in the data read from the volatile memory; 
 correcting the 2-bit error based on the hint data and the data read from the volatile memory to obtain corrected data; and 
 providing the corrected data to the host. 
 
     
     
       19. The method of  claim 18 , further comprising:
 backing up the data read from the volatile memory after the 2-bit error is detected; 
 transferring the first test pattern data, a first write command, and the address to the volatile memory to store the first test pattern data in the volatile memory; 
 transferring a second read command and the address to the volatile memory to acquire the first test data from the volatile memory; 
 transferring the second test pattern data, a second write command, and the address to the volatile memory to store the second test pattern data in the volatile memory; 
 transferring a third read command and the address to the volatile memory to acquire the second test data from the volatile memory; 
 generating result data by performing an XOR operation on the first test data and the second test data; and 
 generating the hint data according to a value of the result data. 
 
     
     
       20. The method of  claim 19 , wherein the correcting of the 2-bit error comprises:
 outputting data in which at least one error bit is corrected by performing the XOR operation on the data read from the volatile memory and the hint data; 
 generating syndrome data based on the data in which the at least one error bit is corrected; 
 calculating coefficients of an error location equation based on a reciprocal of a position of an error bit based on the syndrome data; 
 calculating a position of the error bit in the data in which the at least one error bit is corrected by using the syndrome data and the coefficients of the error location equation; 
 correcting an error by inverting a value of the error bit based on the position; and 
 outputting the corrected data.