Electronic device and phase detector

Abstract

An electronic device and phase detector are provided. The phase detector includes a first input terminal, a second input terminal, a first input buffer, and a second input buffer. The first input buffer is electrically connected to the first input terminal. The second input buffer is electrically connected to the second input terminal.

What is claimed is: 
     
       1. A phase detector, comprising:
 a first input terminal; 
 a second input terminal; 
 a first input buffer electrically connected to the first input terminal; 
 a second input buffer electrically connected to the second input terminal, wherein the first input buffer is configured to receive a feedback signal and generate a first signal and a second signal, wherein the first input terminal is configured to receive the first signal; 
 a first transistor having a gate as the first input terminal, a source electrically connected to a ground; 
 a second transistor having a gate configured to receiving the second signal, a source electrically connected to a supply voltage, and a drain electrically connected to a drain of the first transistor, wherein the second input buffer is configured to receive a reference signal and generate a third signal and a fourth signal, wherein the second input terminal is configured to receive the third signal; 
 a third transistor having a gate as the second input terminal, a source electrically connected to the ground; and 
 a fourth transistor having a gate configured to receiving the second signal, a source electrically connected to the supply voltage, and a drain electrically connected to a drain of the third transistor. 
 
     
     
       2. The phase detector of  claim 1 , wherein the fourth transistor is configured to:
 (i) during the equalization period, be turned on to electrically connect the drain of the third transistor to the supply voltage; and 
 (ii) during the sensing period, be turned off to electrically disconnect the drain of the first transistor from the supply voltage. 
 
     
     
       3. The phase detector of  claim 2 , wherein the second input buffer comprises a fourth inverter, a fifth inverter, and a sixth inverter, wherein the fourth inverter has an input port configured to receive the feedback signal and an output port electrically connected to input ports of the fifth inverter and the sixth inverter. 
     
     
       4. The phase detector of  claim 3 , wherein the second input buffer is configured to provide the third signal to the second input terminal through an output port of the fifth inverter and provide the fourth signal to a dummy load through an output port of the sixth inverter. 
     
     
       5. The phase detector of  claim 2 , further comprising:
 a fifth transistor having a drain as a first output terminal, a source electrically connected to the drain of the first transistor; and 
 a sixth transistor having a gate electrically connected to the first output terminal, a drain as a second output terminal, a source electrically connected to the drain of the third transistor, 
 wherein the fifth transistor has a gate electrically connected to the second output terminal. 
 
     
     
       6. The phase detector of  claim 5 , wherein the first signal and the third signal have the same frequency, and wherein the first signal has a first phase and the third signal has a second phase. 
     
     
       7. The phase detector of  claim 6 , wherein, during the sensing period, if the first phase of the first signal is ahead of the second phase of the third signal, the first transistor and the fifth transistor pull down a voltage at the first output terminal to the ground. 
     
     
       8. The phase detector of  claim 6 , wherein, during the sensing period, if the first phase of the first signal is later than the second phase of the third signal, the third transistor and the sixth transistor pull down a voltage at the second output terminal to a ground. 
     
     
       9. The phase detector of  claim 5 , further comprising:
 a seventh transistor having a gate configured to receiving the second signal, a source electrically connected to the supply voltage, and a drain electrically connected to the first output terminal, 
 wherein the seventh transistor is configured to: 
 (i) during the equalization period, be turned on to electrically connect the first output terminal to the supply voltage; and 
 (ii) during the sensing period, be turned off to electrically disconnect the first output terminal from the supply voltage.