Hybrid metallic structures in stacked semiconductor devices and associated systems and methods

Abstract

A stacked semiconductor device having hybrid metallic structures and associated systems and methods are disclosed herein. The stacked semiconductor device can include a first semiconductor die and a second semiconductor die. The first semiconductor die can include a top surface, a first bond site at the top surface and a second bond site at the first surface spaced apart from the first bond site. The second semiconductor die can include a lower surface facing the top surface of the first semiconductor die, a third bond site at the lower surface, and a fourth bond site at the lower surface. The third bond site includes a conductive structure bonded to the first bond site by a metal-metal bond. The fourth bond site at the lower surface includes a solder ball bonded to the second bond site.

We claim: 
     
       1. A stacked semiconductor device, comprising:
 a first semiconductor die having a first bonding surface, a plurality of first bond sites in a first array on the first bonding surface, and a plurality of second bond sites in a second array on the first bonding surface, wherein the plurality of first bond sites includes a plurality of first bond pads extending to a height, wherein each of the plurality of first bond sites is bonded to a TSV in the first semiconductor die, and wherein the plurality of second bond sites includes a plurality of second bond pads extending to the height; 
 a second semiconductor die having a second bonding surface facing the first bonding surface of the first semiconductor die, a plurality of third bond sites in the first array on the second bonding surface, and a plurality of fourth bond sites in the second array at the second bonding surface, wherein each of the plurality of third bond sites is bonded to a TSV in the second semiconductor die; 
 a plurality of solder-free interconnect structures between the first semiconductor die and the second semiconductor die, wherein each solder-free interconnect structure forms an electrical connection between an individual bond site in the plurality of first bond sites and an individual bond site in the plurality of third bond sites; and 
 a plurality of solder joints between the first semiconductor die and the second semiconductor die, wherein each solder joint is coupled to an individual bond site in the plurality of second bond sites and an individual bond site in the plurality of fourth bond sites. 
 
     
     
       2. The stacked semiconductor device of  claim 1  wherein each solder-free interconnect structure forms a metal-metal bond between the individual bond site in the plurality of first bond sites and the individual bond site in the plurality of third bond sites. 
     
     
       3. The stacked semiconductor device of  claim 1  wherein the electrical connection between the plurality of first bond sites and the plurality of third bond sites establish a plurality of electrical communication channels between the first semiconductor die and the second semiconductor die. 
     
     
       4. The stacked semiconductor device of  claim 1  wherein each bond site in the plurality of second bond sites is bonded to a thermal structure in the first semiconductor die. 
     
     
       5. The stacked semiconductor device of  claim 1  wherein the plurality of solder joints between the plurality of second bond sites and the plurality of fourth bond sites establish a plurality of thermal channels between the first semiconductor die and the second semiconductor die. 
     
     
       6. The stacked semiconductor device of  claim 1  wherein:
 the second semiconductor die has a third bonding surface opposite the second bonding surface, a plurality of fifth bond sites in the first array on the third bonding surface, and a plurality of sixth bond sites in the second array at the third bonding surface, wherein:
 one or more bond sites in the plurality of fifth bond sites is electrically connected to a corresponding bond site in the plurality of third bond sites through an interconnect structure extending through the second semiconductor die, and 
 one or more bond sites in the plurality of sixth bond sites is thermally connected to a corresponding bond site in the plurality of fourth bond sites through a thermal structure extending through the second semiconductor die. 
 
 
     
     
       7. The stacked semiconductor device of  claim 6 , further comprising:
 a third semiconductor die having a fourth bonding surface facing the third bonding surface of the second semiconductor die, a plurality of seventh bond sites in the first array on the fourth bonding surface, and a plurality of eighth bond sites in the second array at the fourth bonding surface, wherein:
 each bond site in the plurality of seventh bond sites includes a conductive structure directly bonded to a corresponding conductive structure in the plurality of fifth bond sites, and 
 each bond site in the plurality of eighth bond sites includes a solder structure bonded to a corresponding conductive structure in the plurality of sixth bond sites. 
 
 
     
     
       8. A method for forming a stacked semiconductor device, comprising:
 forming a conductive pad on at least one first bond site of a first semiconductor die, wherein the at least one first bond site is coupled to a first TSV in the first semiconductor die; 
 forming a solder structure on at least one second bond site of the first semiconductor die adjacent the at least one first bond site, wherein the at least one second bond site is coupled to a second TSV in the first semiconductor die; 
 stacking the first semiconductor die on a second semiconductor die, the second semiconductor die having corresponding conductive pads individually corresponding to each of the at least one first bond site and the at least one second bond site, wherein each of the corresponding conductive pads extends to a matching height above a surface of the second die, and wherein each of the corresponding conductive pads is coupled to an individual TSV in the second die; and 
 bonding the at least one first bond site and the at least one second bond site to the corresponding conductive pads on the second semiconductor die, wherein the bonding includes:
 reflowing the solder structure on the at least one second bond site to bond the at least one second bond site to the corresponding conductive pad on the second semiconductor die; and 
 annealing the conductive pad to form a solder-free interconnect structure forming an electrical connection between the at least one first bond site on the first semiconductor die and the corresponding conductive pad on the second semiconductor die. 
 
 
     
     
       9. The method of  claim 8  wherein the at least one first bond site of the first semiconductor die is at least two first bond sites, and wherein forming the conductive pads on the at least two first bond sites includes:
 disposing a photoresist material over a bonding surface of the first semiconductor die; 
 patterning the photoresist material to expose the at least two first bond sites; 
 depositing a conductive material into the patterned photoresist material beyond a uniform height for the conductive pads; 
 removing the conductive material until each of the conductive pads is at the uniform height; and 
 stripping the photoresist material from the first semiconductor die. 
 
     
     
       10. The method of  claim 9  wherein the at least one second bond site of the first semiconductor die is at least two second bond sites, and wherein forming the solder structures on the at least two second bond sites includes:
 disposing a second photoresist material over the bonding surface of the first semiconductor die and the conductive pads on the at least two first bond sites; 
 patterning the second photoresist material to expose the at least two second bond sites; 
 depositing solder material into the second patterned photoresist material; 
 stripping the second photoresist material from the first semiconductor die; and 
 at least partially reflowing the solder material on the at least two second bond sites. 
 
     
     
       11. The method of  claim 8  wherein the conductive pad on the at least one first bond site of the first semiconductor die and the corresponding conductive pad on the second semiconductor die are both copper pads, and wherein the annealing forms a copper-copper bond between the copper pads.