Integrated circuitry, memory arrays comprising strings of memory cells, methods used in forming integrated circuitry, and methods used in forming a memory array comprising strings of memory cells

Abstract

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed.

The invention claimed is: 
     
       1. Integrated circuitry comprising:
 a three-dimensional (3D) array comprising tiers of electronic components; 
 a stair-step structure laterally-adjacent the 3D array, the stair-step structure having steps individually comprising a tread and a riser; and 
 insulating material atop individual of the treads and aside individual of the risers, the insulating material comprising:
 touching insulative physical objects having void-spaces there-among, the insulative physical objects individually having at least one of a maximum submicron dimension or a minimum submicron dimension, a plurality of the insulative physical objects being both vertically and laterally offset relative to one another, the insulative physical objects comprising at least one of (a) or (b), where: 
 (a): nanowires having two straight-line dimensions therethrough from 1 to 100 nanometers and an aspect ratio of 100 to 1,000; and 
 (b): nanorods having two straight-line dimensions therethrough from 1 to 100 nanometers and an aspect ratio of 2 to 99; and 
 solid insulative material in the void-spaces. 
 
 
     
     
       2. The integrated circuitry of  claim 1  wherein the insulative physical objects comprise the (a). 
     
     
       3. The integrated circuitry of  claim 1  wherein the insulative physical objects comprise a combination of the (a) and the (b). 
     
     
       4. The integrated circuitry of  claim 1  wherein the insulative physical objects and the solid insulative material comprise the same composition relative one another. 
     
     
       5. The integrated circuitry of  claim 1  wherein the insulative physical objects and the solid insulative material comprise different compositions relative one another. 
     
     
       6. The integrated circuitry of  claim 1  wherein the insulative physical objects are crystalline and the solid insulative material is amorphous. 
     
     
       7. The integrated circuitry of  claim 6  wherein the insulative physical objects and the solid insulative material comprise the same composition relative one another. 
     
     
       8. The integrated circuitry of  claim 6  wherein the insulative physical objects and the solid insulative material different compositions relative one another. 
     
     
       9. The memory array of  claim 1  wherein some but not all immediately-adjacent of the physical objects touch one another. 
     
     
       10. The integrated circuitry of  claim 1  wherein the insulative physical objects comprise the (b). 
     
     
       11. The integrated circuitry of  claim 1  wherein the insulative physical objects comprise only one of the (a) and the (b). 
     
     
       12. A memory array comprising strings of memory cells, comprising:
 laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region; 
 the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from the memory-array region into a stair-step region that is adjacent the memory-array region, the insulative tiers and the conductive tiers of the memory blocks in the stair-step region comprising stair-step structures that are laterally-spaced relative one another the stair-step structures individually having steps individually comprising a tread and a riser; 
 insulating material atop individual of the treads and aside individual of the risers, the insulating material comprising:
 touching insulative physical objects having void-spaces there-among, the insulative physical objects individually having at least one of a maximum submicron dimension or a minimum submicron dimension, a plurality of the insulative physical objects being both vertically and laterally offset relative to one another, the insulative physical objects comprising at least one of (a) or (b), where: 
 (a): nanowires having two straight-line dimensions therethrough from 1 to 100 nanometers and an aspect ratio of 100 to 1,000; and 
 (b): nanorods having two straight-line dimensions therethrough from 1 to 100 nanometers and an aspect ratio of 2 to 99; and 
 solid insulative material in the void-spaces. 
 
 
     
     
       13. The memory array of  claim 12  wherein memory array and the strings comprising NAND. 
     
     
       14. The memory array of  claim 12  wherein some but not all immediately-adjacent of the physical objects touch one another. 
     
     
       15. The memory array of  claim 12  wherein the insulative physical objects comprise the (a). 
     
     
       16. The memory array of  claim 12  wherein the insulative physical objects comprise the (b). 
     
     
       17. The memory array of  claim 12  wherein the insulative physical objects comprise the (a) and the (b). 
     
     
       18. The memory array of  claim 12  wherein the insulative physical objects comprise only one of the (a) and the (b).