Device and method for detecting defects on wafer

Abstract

Disclosed is a wafer defect inference system, which includes a test equipment that receives a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit pattern on the semiconductor wafer and combines the first image and the second image to generate a combination image, and at least one computing device that is capable of communicating with the test equipment and infers a defect associated with the circuit pattern formed on the semiconductor wafer. The computing device receives the combination image, performs machine learning for inferring the defect based on the combination image, and generates an output image including information about the defect based on the machine learning.

What is claimed is: 
     
       1. A wafer defect inference system comprising:
 a test equipment configured to receive a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit patterns on the semiconductor wafer and to combine the first image and the second image to generate a combination image; and 
 at least one computing device configured to communicate with the test equipment and configured to infer a defect associated with the circuit pattern formed on the semiconductor wafer based on the combination image, 
 wherein the at least one computing device is configured to:
 receive the combination image; 
 perform machine learning for inferring the defect based on the combination image; and 
 generate an output image including information about the defect based on the machine learning, 
 
 wherein the inferring the defect by performing the machine learning is based on an association between the defect in the circuit pattern and the layout image determined by the machine learning. 
 
     
     
       2. The wafer defect inference system of  claim 1 , wherein the machine learning is based on a generative adversarial network (GAN). 
     
     
       3. The wafer defect inference system of  claim 1 , wherein the machine learning is based on a conditional generative adversarial network (CGAN). 
     
     
       4. The wafer defect inference system of  claim 1 , wherein the test equipment generates the combination image by aligning the first image and the second image around a pattern axis and combining the first image and the second image. 
     
     
       5. The wafer defect inference system of  claim 1 , wherein the at least one computing device includes:
 at least one neuromorphic processor configured to perform the machine learning, to infer the defect, and to generate the output image; 
 a processor configured to control the neuromorphic processor; 
 a random access memory used as a working memory of the neuromorphic processor; and 
 storage configured to store data generated by the processor. 
 
     
     
       6. The wafer defect inference system of  claim 5 , wherein the neuromorphic processor is configured to
 generate a fake combination image based on an input vector; and 
 determine whether the combination image or the fake combination image is real or fake. 
 
     
     
       7. The wafer defect inference system of  claim 6 , wherein the neuromorphic processor is configured to
 perform a first machine learning for determining whether the combination image or the fake combination image is real or fake, and 
 perform a second machine learning for generating the fake combination image for training of the first machine learning. 
 
     
     
       8. The wafer defect inference system of  claim 1 , wherein the at least one computing device generates the output image based on at least one of a segmentation model, a heat map model, or a combination model corresponding to a combination of the segmentation model and the heat map model. 
     
     
       9. The wafer defect inference system of  claim 1 , wherein the information about the defect includes at least one of a location of the defect, a size of the defect, a color of the defect, or a kind of the defect. 
     
     
       10. A method of inferring a defect in a circuit pattern formed on a semiconductor wafer, the method comprising:
 combining a first image and a second image to generate a combination image by overlapping the first image and the second image around a pattern axis, the first image including an imaging of the circuit pattern, and the second image including an imaging of a layout image of a mask for implementing the circuit pattern on the semiconductor wafer; 
 generating, based on a machine learning operation of at least one computing device, an output image from the combination image, the output image including defect information about the defect; and 
 outputting the output image, 
 wherein the generating the output image includes inferring, by the machine learning operation, the defect based on an association between the defect in the circuit pattern and the layout image. 
 
     
     
       11. The method of  claim 10 , wherein the machine learning operation is based on a generative adversarial network (GAN). 
     
     
       12. The method of  claim 10 , wherein the machine learning operation is based on a conditional generative adversarial network (CGAN). 
     
     
       13. The method of  claim 10 , wherein the machine learning includes a first machine learning and a second machine learning,
 the first machine learning is performed by a discriminator network to determine whether an input image is real or fake, and 
 the second machine learning is performed by a generator network to generate a fake combination image which is determined as real by the discriminator network. 
 
     
     
       14. The method of  claim 10 , wherein the output image is generated based on at least one of a segmentation model, a heat map model, or a combination model corresponding to a combination of the segmentation model and the heat map model. 
     
     
       15. The method of  claim 10 , wherein the defect information includes at least one of a location of the defect, a size of the defect, a color of the defect, or a kind of the defect. 
     
     
       16. A non-transitory computer-readable medium storing a program code including an image generation model executable by a processor, the program code, when executed, causing the processor to:
 combine a first image and a second image to generate a combination image, the first image including an imaging of a circuit pattern formed on a semiconductor wafer, and the second image including an imaging of a layout image of a mask for implementing the circuit pattern on the semiconductor wafer; and 
 generate, based on machine learning, an output image from the combination image, the output image including defect information of the circuit pattern, 
 wherein the generating the output image includes inferring, by the machine learning, the defect based on an association between the defect in the circuit pattern and the layout image. 
 
     
     
       17. The non-transitory computer-readable medium of  claim 16 , wherein the machine learning is based on a generative adversarial network (GAN). 
     
     
       18. The non-transitory computer-readable medium of  claim 16 , wherein the machine learning is based on a conditional generative adversarial network (CGAN). 
     
     
       19. The non-transitory computer-readable medium of  claim 16 , wherein the output image is generated based on at least one of a segmentation model, a heat map model, or a combination model corresponding to a combination of the segmentation model and the heat map model.