Memory and operation method of memory with repairing and random pulse generating capability

Abstract

A method for operating a memory includes: receiving an active command and a row address; confirming that a portion of columns of a first row corresponding to the row address is replaced with a portion of columns of a second row; activating the first row and the second row; confirming activation of a random pulse; randomly selecting one among the row address corresponding to the first row and a row address corresponding to the second row in response to the activation of the random pulse; and sampling the selected row address as a sampling address.

What is claimed is: 
     
       1. A method for operating a memory, the method comprising:
 receiving an active command and a row address for a first row; 
 confirming that a portion of columns of the first row is replaced with a portion of columns of a second row; 
 activating the first row and the second row in response to the active command for the first row; 
 confirming activation of a random pulse; 
 selecting a row address corresponding to the first row when a number of times that the first row is activated during the activation of the random pulse is one of odd and even numbers; 
 selecting a row address corresponding to the second row when the number is the other one of the odd and even numbers; and 
 sampling the selected row address as a sampling address. 
 
     
     
       2. The method of  claim 1 , further comprising:
 determining to perform a smart refresh operation; and 
 refreshing a neighboring row which is positioned adjacent to a row corresponding to the sampling address. 
 
     
     
       3. The method of  claim 1 , wherein the randomly selecting includes:
 counting a number of times that the active command is applied during an activation period of the random pulse; 
 selecting the row address corresponding to the first row address when the number is an even number, and selecting the row address corresponding to the second row address when the number is an odd number; and 
 storing the selected row address as the sampling address. 
 
     
     
       4. A memory, comprising:
 a cell array including a plurality of memory cells that are arranged in a plurality of rows and a plurality of columns; 
 a repair circuit suitable for: 
 storing information about at least one defective rows having a failure in a portion of columns among the rows, and 
 activating a repair signal and providing an additional active address representing a row that is to be activated additionally in response to an active command provided together with an active address for the defective row; 
 a random pulse generation circuit suitable for generating a random pulse signal that is randomly activated; and 
 a sampling circuit suitable for sampling and storing: 
 the active address when the active signal and the random pulse signal are activated and the repair signal is deactivated, 
 the active address when a number of times that the active signal is activated in an activation period of the random pulse signal is one of odd and even numbers and when the active signal, the random pulse signal and the repair signal are activated, and 
 the additional active address when the number is the other one of the odd and even numbers and when the active signal, the random pulse signal and the repair signal are activated. 
 
     
     
       5. The memory of  claim 4 , further comprising a row circuit suitable for activating a row corresponding to the active address among the rows of the cell array when the active signal is activated, and
 activating a row corresponding to the additional active address together with the row corresponding to the active address among the rows of the cell array when the repair signal is activated. 
 
     
     
       6. The memory of  claim 5 , wherein the row circuit is further suitable for accessing, when the row corresponding to the active address and the row corresponding to the additional active address are activated in the cell array, one among the two activated rows based on a column address during read and write operations. 
     
     
       7. The memory of  claim 5 , further comprising a smart refresh circuit suitable for controlling the row circuit to refresh a neighboring row of a row corresponding to an address stored in the sampling circuit during a smart refresh operation. 
     
     
       8. An operating method of a memory, the operating method comprising:
 activating, among rows of memory cells, first and second rows in response to an active command for activating the first row; 
 selecting one of the first and second rows based on whether odd or even is a number of times that the active command is provided during a random time amount; and 
 refreshing, among the rows of memory cells, one or more rows adjacent to the selected row, 
 wherein at least one memory cell in the first row is replaced with a corresponding memory cell in the second row according to a paired row repair scheme.