Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

What is claimed is: 
     
       1. A silicon carbide semiconductor device, comprising:
 a silicon carbide semiconductor substrate of a first conductivity type, having a first surface and a second surface opposite to each other; 
 a first semiconductor layer of the first conductivity type, provided on the first surface of the silicon carbide semiconductor substrate, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the first semiconductor layer facing the silicon carbide semiconductor substrate; 
 a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the silicon carbide semiconductor substrate; 
 a third semiconductor layer of the first conductivity type, selectively provided at the first surface of the second semiconductor layer, the third semiconductor layer having a first surface and a second surface opposite to each other, the second surface facing the silicon carbide semiconductor substrate; 
 a first semiconductor region of the first conductivity type, selectively provided at the first surface of the third semiconductor layer; 
 a second semiconductor region of the second conductivity type, selectively provided in the third semiconductor layer, the second semiconductor region penetrating through the third semiconductor layer from the first surface of the third semiconductor layer, and having an impurity concentration higher than an impurity concentration of the second semiconductor layer; 
 a trench penetrating through the first semiconductor region, the second semiconductor layer, and the third semiconductor layer, and reaching the first semiconductor layer; 
 a gate electrode provided in the trench via a gate insulating film; 
 an interlayer insulating film provided on the gate electrode; 
 a first electrode provided on the first surface of the second semiconductor layer and a surface of the first semiconductor region; and 
 a second electrode provided on the second surface of the silicon carbide semiconductor substrate, wherein 
 the first semiconductor region has an impurity concentration that gradually decreases closer to the third semiconductor layer, 
 the third semiconductor layer has an impurity concentration that is substantially constant, and 
 the first semiconductor region is thinner than a portion of the third semiconductor layer that is between the first semiconductor region and the second semiconductor layer. 
 
     
     
       2. The silicon carbide semiconductor device according to  claim 1 , wherein
 the impurity concentration of the first semiconductor region has a maximum value in a range from 1.0×10 18 /cm 3  to 5.0×10 19 /cm 3 . 
 
     
     
       3. The silicon carbide semiconductor device according to  claim 1 , wherein
 the third semiconductor layer has an impurity concentration that is in a range from 1.0×10 16 /cm 3  to 1.0×10 18 /cm 3 . 
 
     
     
       4. The silicon carbide semiconductor device according to  claim 1 , wherein
 the first semiconductor region has a high-concentration portion at the first surface of the third semiconductor layer and a low-concentration portion facing the silicon carbide semiconductor substrate. 
 
     
     
       5. A method of manufacturing a silicon carbide semiconductor device, the method comprising:
 preparing a silicon carbide semiconductor substrate of a first conductivity type, the silicon carbide semiconductor substrate having a first surface and a second surface opposite to each other, and forming a first semiconductor layer of the first conductivity type on the first surface of the silicon carbide semiconductor substrate, the first semiconductor layer having an impurity concentration that is lower than an impurity concentration of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the first semiconductor layer facing the silicon carbide semiconductor substrate; 
 forming a second semiconductor layer of a second conductivity type on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the silicon carbide semiconductor substrate; 
 forming, by epitaxial growth, a third semiconductor layer of the first conductivity type at the first surface of the second semiconductor layer, the third semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the third semiconductor layer facing the silicon carbide semiconductor substrate; 
 selectively forming a first semiconductor region of the first conductivity type by implanting an impurity of the first conductivity type at the first surface of the third semiconductor layer; 
 implanting an impurity of the second conductivity type at the first surface of the third semiconductor layer to thereby selectively form a second semiconductor region of the second conductivity type, the second semiconductor region penetrating through the third semiconductor layer and having an impurity concentration higher than an impurity concentration of the second semiconductor layer; 
 forming a trench penetrating through the first semiconductor region, the second semiconductor layer, and the third semiconductor layer, and reaching the first semiconductor layer; 
 forming a gate electrode in the trench via a gate insulating film; 
 forming an interlayer insulating film on the gate electrode; 
 forming a first electrode on the first surface of the second semiconductor layer and a surface of the first semiconductor region; and 
 forming a second electrode on the second surface of the silicon carbide semiconductor substrate, wherein 
 the first semiconductor region has an impurity concentration that gradually decreases closer to the third semiconductor layer, 
 the third semiconductor layer has an impurity concentration that is substantially constant, and 
 the first semiconductor region is formed to be thinner than a portion of the third semiconductor layer that is between the first semiconductor region and the second semiconductor layer. 
 
     
     
       6. The method according to  claim 5 , wherein
 forming the first semiconductor region includes implanting phosphorus or nitrogen as the impurity of the first conductivity type. 
 
     
     
       7. The method according to  claim 5 , wherein
 forming the first semiconductor region includes forming the first semiconductor region so that a maximum impurity concentration of the first semiconductor region is in a range from 1.0×10 18 /cm 3  to 5.0×10 19 /cm 3 . 
 
     
     
       8. The method according to  claim 5 , wherein
 forming the third semiconductor layer includes forming the third semiconductor layer to have an impurity concentration that is in a range from 1.0×10 16 /cm 3  to 1.0×10 18 /cm 3 . 
 
     
     
       9. The method according to  claim 5 , wherein
 selectively forming the first semiconductor region includes forming the first semiconductor region to have a two-layer structure including a high-concentration portion at the first surface of the third semiconductor layer and a low-concentration portion facing the silicon carbide semiconductor substrate.