Semiconductor device including ferroelectric layer and insulation layer with metal particles and methods of manufacturing the same

Abstract

A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate, a gate insulation layer disposed on the ferroelectric layer, metal particles disposed in the gate insulation layer, and a gate electrode layer disposed on the gate insulation layer.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a substrate; 
 a ferroelectric layer disposed on the substrate; 
 a gate insulation layer disposed on the ferroelectric layer; 
 metal particles disposed in the gate insulation layer; and 
 a gate electrode layer disposed on the gate insulation layer, 
 wherein the metal particles are embedded in an inner region of the gate insulation layer, and 
 wherein the metal particles are distributed on a plane, spaced apart from the ferroelectric layer. 
 
     
     
       2. The semiconductor device of  claim 1 , further comprising a source region and a drain region spaced apart in the substrate. 
     
     
       3. The semiconductor device of  claim 1 , wherein the ferroelectric layer includes at least one oxide selected from the group consisting of hafnium oxide, zirconium oxide, and hafnium zirconium oxide. 
     
     
       4. The semiconductor device of  claim 3 , wherein the ferroelectric layer includes at least one dopant, and
 wherein the dopant includes at least one selected from the group consisting of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La). 
 
     
     
       5. The semiconductor device of  claim 1 , wherein the ferroelectric layer includes a metal oxide having a perovskite structure. 
     
     
       6. The semiconductor device of  claim 1 , wherein the metal particles are distributed on the plane spaced apart from an interface between the ferroelectric layer and the gate insulation layer. 
     
     
       7. The semiconductor device of  claim 6 , wherein the plane is parallel to the interface between the ferroelectric layer and the gate insulation layer. 
     
     
       8. The semiconductor device of  claim 1 , wherein the metal particles have a diameter of 0.1 nanometer (nm) to 5 nanometers (nm). 
     
     
       9. The semiconductor device of  claim 1 , wherein the metal particles include at least one selected from the group consisting of cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), and manganese (Mn). 
     
     
       10. The semiconductor device of  claim 1 , wherein the metal particles trap or de-trap electric charges according to a polarity of a voltage applied between the gate electrode layer and the substrate. 
     
     
       11. A semiconductor device comprising:
 a substrate; 
 a channel layer disposed on the substrate; 
 a ferroelectric layer disposed on the channel layer; 
 a gate insulation layer disposed on the ferroelectric layer; 
 metal particles disposed in the gate insulation layer; 
 a gate electrode layer disposed on the gate insulation layer; and 
 a source electrode layer and a drain electrode layer that are disposed over the substrate and that respectively contact opposite ends of the channel layer, 
 wherein the metal particles are embedded in an inner region of the gate insulation layer, and 
 wherein the metal particles are distributed on a plane, spaced apart from the ferroelectric layer. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the metal particles are distributed on the plane spaced apart from an interface between the ferroelectric layer and the gate insulation layer. 
     
     
       13. The semiconductor device of  claim 11 , wherein the metal particles are distributed on the plane that is parallel to an interface between the ferroelectric layer and the gate insulation layer. 
     
     
       14. The semiconductor device of  claim 11 , wherein the metal particles trap or de-trap electric charges according to a polarity of a voltage applied between the gate electrode layer and the substrate. 
     
     
       15. A semiconductor device comprising:
 a substrate; 
 a gate structure including a hole pattern disposed over the substrate, the gate structure including gate electrode layers and interlayer insulation layers that are alternately stacked; 
 a gate insulation layer disposed on a sidewall surface of the gate structure exposed by the hole pattern; 
 metal particles distributed in the gate insulation layer; 
 a ferroelectric layer disposed on the gate insulation layer; and 
 a channel layer disposed on the ferroelectric layer, 
 wherein the metal particles are embedded in an inner region of the gate insulation layer, and 
 wherein the metal particles are distributed on a plane, spaced apart from the ferroelectric layer. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the channel layer extends in a direction substantially perpendicular to an upper surface of the substrate. 
     
     
       17. The semiconductor device of  claim 15 , further comprising a source line and a bit line electrically connected to opposite ends of the channel layer. 
     
     
       18. The semiconductor device of  claim 15 , wherein the metal particles are distributed on the plane spaced apart from an interface of the ferroelectric layer and the gate insulation layer. 
     
     
       19. The semiconductor device of  claim 18 , wherein the plane is parallel to the interface of the ferroelectric layer and the gate insulation layer. 
     
     
       20. The semiconductor device of  claim 15 , wherein the metal particles have a diameter of 0.1 nanometer (nm) to 5 nanometers (nm). 
     
     
       21. The semiconductor device of  claim 15 , wherein the metal particles include at least one selected from the group consisting of cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), and manganese (Mn). 
     
     
       22. The semiconductor device of  claim 15 , wherein the metal particles trap or de-trap electric charges according to a polarity of a voltage applied between the gate electrode layers and the channel layer.