Resonant filter for solid state RF impedance matching network

Abstract

In one embodiment, an RF impedance matching circuit includes at least one electronically variable capacitor (EVC) comprising discrete fixed capacitors. Each fixed capacitor has a corresponding switching circuit for switching in and out the fixed capacitor to alter a total capacitance of the EVC. Each switching circuit includes a diode operably coupled to the fixed capacitor to cause the switching in and out of the fixed capacitor, the diode being a PIN diode or an NIP diode. Each switching circuit further includes a driver circuit operably coupled to the diode, and a resonant filter positioned between the driver circuit and the diode. The resonant filter includes an inductor and a capacitor coupled in parallel.

What is claimed is: 
     
       1. A radio frequency (RF) impedance matching circuit comprising:
 an RF input configured to operably couple to an RF source providing an RF signal; 
 an RF output configured to operably couple to a plasma chamber; 
 at least one electronically variable capacitor (EVC) comprising discrete fixed capacitors, each fixed capacitor of each EVC having a corresponding switching circuit for switching in and out the fixed capacitor to alter a total capacitance of the EVC; and 
 a control circuit configured to cause the switching in and out of the fixed capacitors of each EVC to enable an impedance match; 
 wherein each switching circuit for each fixed capacitor of each EVC comprises:
 a diode operably coupled to the fixed capacitor to cause the switching in and out of the fixed capacitor, the diode being a PIN diode or an NIP diode; 
 a driver circuit comprising:
 a first power switch configured to receive a reverse bias voltage and switchably connect the reverse bias voltage to a common output in response to a received input signal; and 
 a second power switch configured to receive a forward bias voltage and switchably connect the forward bias voltage to the common output in response to a received input signal, the common output being directly coupled to both an output of the first power switch and an output of the second power switch; and 
 
 a resonant filter comprising:
 an inductor; 
 a capacitor coupled in parallel with the inductor; 
 a first terminal coupled to the common output; and 
 a second terminal, distinct from the first terminal of the resonant filter, coupled to a node between the fixed capacitor and the diode. 
 
 
 
     
     
       2. The matching circuit of  claim 1  wherein each EVC is configured such that, when any of the fixed capacitors switches out, the switching occurs in 100 microseconds or less. 
     
     
       3. The matching circuit of  claim 1  wherein each EVC is configured such that, when any of the fixed capacitors switches out, the switching occurs in 200 microseconds or less. 
     
     
       4. The matching circuit of  claim 1  wherein the RF source is configured to provide at least two repeating, non-zero pulse levels. 
     
     
       5. The matching circuit of  claim 4 :
 wherein, by the switching in or out of the fixed capacitors, each EVC is configured to switch between a plurality of match configurations for enabling the impedance match and thereby reducing a reflected power at an output of the RF source as the variable impedance of the plasma chamber changes; and 
 wherein, for each of the pulse levels, the control circuit is configured to determine, from the plurality of match configurations, a new match configuration to enable the impedance match. 
 
     
     
       6. The matching circuit of  claim 1  wherein to switch the switching circuit ON and thereby switch in the corresponding fixed capacitor, a DC current flows from the forward bias voltage through the diode. 
     
     
       7. The matching circuit of  claim 6  wherein the forward bias voltage and the diode are coupled to a common ground. 
     
     
       8. The matching circuit of  claim 1  wherein the first power switch comprises a MOSFET, and the second power switch comprises a MOSFET. 
     
     
       9. The matching circuit of  claim 1  wherein when the first power switch is open, the second power switch is closed, and when the first power switch is closed, the second power is open. 
     
     
       10. A semiconductor processing tool comprising:
 a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and 
 an impedance matching circuit operably coupled to the plasma chamber, the matching circuit comprising:
 an RF input configured to operably couple to an RF source providing an RF signal; 
 an RF output configured to operably couple to the plasma chamber; 
 at least one electronically variable capacitor (EVC) comprising discrete fixed capacitors, each fixed capacitor of each EVC having a corresponding switching circuit for switching in and out the fixed capacitor to alter a total capacitance of the EVC; and 
 a control circuit configured to cause the switching in and out of the fixed capacitors of each EVC to enable an impedance match; 
 wherein each switching circuit for each fixed capacitor of each EVC comprises:
 a diode operably coupled to the fixed capacitor to cause the switching in and out of the fixed capacitor, the diode being a PIN diode or an NIP diode; 
 a driver circuit comprising:
 a first power switch configured to receive a reverse bias voltage and switchably connect the reverse bias voltage to a common output in response to a received input signal; and 
 a second power switch configured to receive a forward bias voltage and switchably connect the forward bias voltage to the common output in response to a received input signal, the common output being directly coupled to both an output of the first power switch and an output of the second power switch; and 
 
 a resonant filter comprising:
 an inductor; 
 a capacitor coupled in parallel with the inductor; 
 a first terminal coupled to the common output; and 
 a second terminal, distinct from the first terminal of the resonant filter, coupled to a node between the fixed capacitor and the diode. 
 
 
 
 
     
     
       11. The processing tool of  claim 10  wherein each EVC is configured such that, when any of the fixed capacitors switches out, the switching occurs in 100 microseconds or less. 
     
     
       12. The processing tool of  claim 10  wherein each EVC is configured such that, when any of the fixed capacitors switches out, the switching occurs in 200 microseconds or less. 
     
     
       13. A method of fabricating a semiconductor, the method comprising:
 placing a substrate in a plasma chamber configured to deposit a material layer on the substrate or etch a material layer from the substrate; 
 energizing plasma within the plasma chamber by coupling RF power from an RF source to the plasma chamber to perform the deposition or etching; and 
 while energizing the plasma, carrying out an impedance match by an impedance matching circuit coupled between the plasma chamber and the RF source, the matching circuit comprising:
 an RF input configured to operably couple to the RF source; 
 an RF output configured to operably couple to the plasma chamber; 
 at least one electronically variable capacitor (EVC) comprising discrete fixed capacitors, each fixed capacitor of each EVC having a corresponding switching circuit for switching in and out the fixed capacitor to alter a total capacitance of the EVC; and 
 a control circuit configured to cause the switching in and out of the fixed capacitors of each EVC to enable an impedance match; 
 wherein each switching circuit for each fixed capacitor of each EVC comprises:
 a diode operably coupled to the fixed capacitor to cause the switching in and out of the fixed capacitor, the diode being a PIN diode or an NIP diode; 
 a driver circuit comprising:
 a first power switch configured to receive a reverse bias voltage and switchably connect the reverse bias voltage to a common output in response to a received input signal; and 
 a second power switch configured to receive a forward bias voltage and switchably connect the forward bias voltage to the common output in response to a received input signal, the common output being directly coupled to both an output of the first power switch and an output of the second power switch; and 
 
 a resonant filter comprising:
 an inductor; 
 a capacitor coupled in parallel with the inductor; 
 a first terminal coupled to the common output; and 
 a second terminal, distinct from the first terminal of the resonant filter, coupled to a node between the fixed capacitor and the diode. 
 
 
 
 
     
     
       14. A method of matching an impedance comprising:
 coupling a radio frequency (RF) input of a matching circuit to an RF source; 
 coupling an RF output of the matching circuit to a plasma chamber, wherein the matching circuit comprises:
 at least one electronically variable capacitor (EVC) comprising discrete fixed capacitors, each fixed capacitor of each EVC having a corresponding switching circuit for switching in and out the fixed capacitor to alter a total capacitance of the EVC; and 
 a control circuit configured to cause the switching in and out of the fixed capacitors of each EVC to enable an impedance match; 
 wherein each switching circuit for each fixed capacitor of each EVC comprises:
 a diode operably coupled to the fixed capacitor to cause the switching in and out of the fixed capacitor, the diode being a PIN diode or an NIP diode; 
 a driver circuit comprising:
 a first power switch configured to receive a reverse bias voltage and switchably connect the reverse bias voltage to a common output in response to a received input signal; and 
 a second power switch configured to receive a forward bias voltage and switchably connect the forward bias voltage to the common output in response to a received input signal, the common output being directly coupled to both an output of the first power switch and an output of the second power switch; and 
 
 a resonant filter comprising:
 an inductor; 
 a capacitor coupled in parallel with the inductor; 
 a first terminal coupled to the common output; and 
 a second terminal, distinct from the first terminal of the resonant filter, coupled to a node between the fixed capacitor and the diode; and 
 
 
 
 matching an impedance by at least one of the switching circuits of the at least one EVC switching in or out its corresponding fixed capacitor to alter a total capacitance of the EVC. 
 
     
     
       15. The method of  claim 14  wherein each EVC is configured such that, when any of the fixed capacitors switches out, the switching occurs in 100 microseconds or less. 
     
     
       16. The method of  claim 14  wherein each EVC is configured such that, when any of the fixed capacitors switches out, the switching occurs in 200 microseconds or less. 
     
     
       17. The method of  claim 14  wherein the RF source is configured to provide at least two repeating, non-zero pulse levels. 
     
     
       18. The method of  claim 17 :
 wherein, by the switching in or out of the fixed capacitors, each EVC is configured to switch between a plurality of match configurations for enabling the impedance match and thereby reducing a reflected power at an output of the RF source as the variable impedance of the plasma chamber changes; and 
 wherein, for each of the pulse levels, the control circuit is configured to determine, from the plurality of match configurations, a new match configuration to enable the impedance match. 
 
     
     
       19. The method of  claim 14  wherein to switch the switching circuit ON and thereby switch in the corresponding fixed capacitor, a DC current flows from the forward bias voltage through the diode. 
     
     
       20. The method of  claim 19  wherein the forward bias voltage and the diode are coupled to a common ground.