Stacked device structures and methods for forming the same

Abstract

A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.

What is claimed is: 
     
       1. A method of making a complementary metal oxide semiconductor (CMOS) device comprising:
 forming a first transistor having a first conductivity type on a first substrate; 
 forming a backside contact to the first transistor by etching a contact via hole in a dielectric layer over the first transistor and depositing a conducting material in the contact via hole; 
 forming a second transistor having a second conductivity type on a second substrate; and 
 bonding the first transistor of the first conductivity type formed on the first substrate to the second transistor of the second conductivity type formed on the second substrate to form the CMOS device by bonding the backside contact of the first transistor to a contact of the second transistor. 
 
     
     
       2. The method of  claim 1 , wherein forming the first transistor comprises forming a gate all around transistor and forming the second transistor comprises forming a fin field effect transistor (FinFET). 
     
     
       3. The method of  claim 2 , wherein bonding the first transistor having a first conductivity type formed on the first substrate to the second transistor having a second conductivity type formed over the second substrate to form the CMOS device comprises:
 bonding a contact via of the transistor of the first type to a back end of the line (BEOL) metal contact of the transistor of the second type. 
 
     
     
       4. The method of  claim 2 , wherein bonding the first transistor having a first conductivity type formed on the first substrate to the second transistor having a second conductivity type formed over the second substrate to form the CMOS device comprises:
 bonding a contact via of the first transistor having a first conductivity type to a bottom contact of the second transistor having a second conductivity type. 
 
     
     
       5. The method of  claim 3 , wherein bonding a contact via of the first transistor of the first conductivity type to a back end of the line (BEOL) metal contact of the second transistor of the second conductivity type comprises bonding the contact via of the first transistor having a first conductivity type to a redistribution layer and bonding the back end of the line (BEOL) metal contact of the second transistor having a second conductivity type to the redistribution layer. 
     
     
       6. The method of  claim 1 , wherein the bonding of the first transistor of the first conductivity type formed on the first substrate to the second transistor of the second conductivity type formed over the second substrate to form the CMOS device comprises hybrid bonding. 
     
     
       7. The method of  claim 1 , further comprising forming at least one redistribution layer between the first transistor having a first conductivity type and the second transistor having a second conductivity type. 
     
     
       8. A method of making a semiconductor device, the method comprising:
 forming a first transistor including a gate stack and a contact via contacting the gate stack; 
 forming a second transistor including a gate stack and an interconnect over the gate stack of the second transistor; and 
 bonding the first transistor to the second transistor such that the contact via of the first transistor is electrically coupled to the interconnect of the second transistor. 
 
     
     
       9. The method of  claim 8 , wherein the bonding the first transistor to the second transistor comprises bonding the first transistor to the second transistor such that the interconnect of the second transistor is between the contact via of the first transistor and the gate stack of the second transistor. 
     
     
       10. The method of  claim 8 , wherein the first transistor further comprises a dielectric layer on the gate stack of the first transistor, the contact via is in the dielectric layer, and the bonding of the first transistor to the second transistor comprises bonding the first transistor to the second transistor such that the dielectric layer is between the second transistor and the gate stack in the first transistor. 
     
     
       11. The method of  claim 8 , wherein the forming of the first transistor comprises forming the first transistor to have a first conductivity type and the forming of the second transistor comprises forming the second transistor to have a second conductivity type different than the first conductivity type. 
     
     
       12. The method of  claim 8 , wherein the forming of the first transistor comprises:
 forming the gate stack of the first transistor on a first substrate; and 
 after removing the first substrate, forming the contact via in contact with the gate stack. 
 
     
     
       13. The method of  claim 8 , wherein the forming of the second transistor comprises forming the second transistor on a second substrate, and the bonding of the first transistor to the second transistor comprises bonding the first transistor to a side of the second transistor opposite the second substrate. 
     
     
       14. The method of  claim 8 , wherein the bonding of the first transistor to the second transistor comprises forming a hybrid bond between the first transistor and the second transistor. 
     
     
       15. A method of making a semiconductor device, the method comprising:
 forming a fin-shaped field effect transistor (FinFET) including an interlayer dielectric (ILD) layer and an interconnect in the ILD layer; 
 forming a gate-all-around field effect transistor (GAAFET) including a gate stack and a contact via contacting the gate stack; and 
 bonding the GAAFET to the FinFET such that the contact via of the GAAFET is electrically coupled to the interconnect of the FinFET. 
 
     
     
       16. The method of  claim 15 , wherein the forming of the GAAFET comprises:
 forming a semiconductor layer comprising an active region adjacent the gate stack; 
 forming a dielectric layer on the gate stack; and 
 forming the contact via in the dielectric layer such that the contact via contacts the active region of the semiconductor layer adjacent the gate stack. 
 
     
     
       17. The method of  claim 16 , wherein the bonding of the GAAFET to the FinFET comprises bonding the contact via of the GAAFET to the interconnect of the FinFET such that the contact via and the dielectric layer are located between the gate stack and the FinFET. 
     
     
       18. The method of  claim 15 , wherein the forming of the FinFET comprises:
 forming a semiconductor layer on a substrate; 
 forming a contact on an active region of the semiconductor layer; 
 forming the interlayer dielectric (ILD) layer on the contact; and 
 forming the interconnect in the ILD layer such that the interconnect is on the contact. 
 
     
     
       19. The method of  claim 18 , wherein the forming of the FinFET further comprises forming a gate stack on a channel region of the semiconductor layer, and the bonding of the GAAFET to the FinFET comprises bonding the contact via of the GAAFET to the interconnect of the FinFET such that the contact via is located over the gate stack of the FinFET. 
     
     
       20. The method of  claim 15 , wherein the bonding of the GAAFET to the FinFET comprises forming a hybrid bond between the GAAFET and the FinFET.