Image stitching method for stitching product

Abstract

The present application discloses an image stitching method for a stitching product, which includes: step 1: providing a chip design layout of the stitching product; step 2: designing a mask layout according to the chip design layout, including: step 21: setting unit mask images; step 22: merging logic images or cutting path images of adjacent areas between unit regions together to set corresponding peripheral mask images; step 23: merging the same peripheral mask images into one; step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; step 3: performing repeated exposure to form the stitching product. The present application can reduce the number of mask images, the number of times of exposure and the time of exposure.

What is claimed is: 
     
       1. An image stitching method for a stitching product, comprising:
 step 1: providing a chip design layout of the stitching product and dividing the chip design layout into unit regions and peripheral regions, each unit region being formed by repeatedly arranging a plurality of unit circuit images, 
 logic regions and cutting paths being provided in the peripheral regions, each logic region comprising a logic image, and each cutting path comprising a cutting path image, 
 adjacent chips of the stitching product being isolated by the cutting paths; 
 step 2: designing a mask layout according to the chip design layout, comprising: 
 step 21: setting unit mask images for defining the unit circuit images; 
 step 22: merging the logic images or cutting path images of adjacent areas between the unit regions together to set corresponding peripheral mask images; 
 step 23: comparing whether the peripheral mask images at symmetrical positions of the unit regions are the same, and merging same peripheral mask images into one; and 
 step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; and 
 step 3: performing repeated exposure to form the stitching product, comprising: 
 performing repeated exposure in the unit regions by adopting the unit mask images until all unit circuit images in the unit regions are defined on the chips; and 
 performing repeated exposure in the peripheral regions by adopting the corresponding peripheral mask images to form each logic image and each cutting path image on the chips, exposed adjacent areas being not exposed any longer in a subsequent exposure process of the chip after each logic image and each cutting path image in the adjacent areas are defined on one of the chips in the adjacent areas between the unit regions of the adjacent chips. 
 
     
     
       2. The image stitching method for the stitching product according to  claim 1 , wherein, in step 1, a top view of each unit region is in a shape of a rectangle; and
 the rectangle of the unit region comprises a first side, a second side, a third side, and a fourth side, the first side and the third side are a pair of parallel opposite sides, and the second side and the fourth side are another pair of parallel opposite sides. 
 
     
     
       3. The image stitching method for the stitching product according to  claim 2 , wherein each unit mask image is in the shape of a rectangle. 
     
     
       4. The image stitching method for the stitching product according to  claim 3 , wherein, in a parallel direction along the first side, a plurality of the unit regions are arranged adjacent, adjacent areas between the adjacent unit regions are first adjacent areas, and the logic images or the cutting path images in the first adjacent areas are merged together to set a first peripheral mask image. 
     
     
       5. The image stitching method for the stitching product according to  claim 4 , wherein, in a parallel direction along the second side, a plurality of the unit regions are arranged adjacent, adjacent areas between the adjacent unit regions are second adjacent areas, and the logic images or the cutting path images in the second adjacent areas are merged together to set a second peripheral mask image. 
     
     
       6. The image stitching method for the stitching product according to  claim 5 , wherein four corners of each unit region have third adjacent areas formed by four adjacent unit regions, and the logic images or the cutting path images in the third adjacent areas are merged together to set a third peripheral mask image. 
     
     
       7. The image stitching method for the stitching product according to  claim 6 , wherein the first peripheral mask image is in the shape of a rectangle, and in the parallel direction along the second side, a size of the first peripheral mask image is the same as a size of the unit mask image. 
     
     
       8. The image stitching method for the stitching product according to  claim 7 , wherein the second peripheral mask image is in the shape of a rectangle, and in the parallel direction along the first side, a size of the second peripheral mask image is the same as the size of the unit mask image. 
     
     
       9. The image stitching method for the stitching product according to  claim 8 , wherein the third peripheral mask image is in the shape of a rectangle,
 in the parallel direction along the first side, a size of the third peripheral mask image is the same as the size of the first peripheral mask image, and 
 in the parallel direction along the second side, the size of the third peripheral mask image is the same as the size of the second peripheral mask image. 
 
     
     
       10. The image stitching method for the stitching product according to  claim 9 , wherein area ranges of the unit mask image, the first peripheral mask image, the second peripheral mask image, and the third peripheral mask image are all smaller than a single exposure range of a lithography machine, and
 a forming area range of the chip is larger than the single exposure range of the lithography machine. 
 
     
     
       11. The image stitching method for the stitching product according to  claim 1 , wherein the chip is a CMOS image sensor chip. 
     
     
       12. The image stitching method for the stitching product according to  claim 11 , wherein the unit region is a pixel region and each unit of the unit region is a pixel unit. 
     
     
       13. The image stitching method for the stitching product according to  claim 11 , wherein a mark image and a test key are provided on the cutting path. 
     
     
       14. The image stitching method for the stitching product according to  claim 13 , wherein the mark image comprises an alignment mark image or an overlay mark image. 
     
     
       15. The image stitching method for the stitching product according to  claim 13 , wherein, in step 3, each chip is formed on a wafer.