Wafer with semiconductor devices and integrated electrostatic discharge protection

Abstract

A wafer includes a substrate that includes a channel layer, a first active region, a second active region, and a saw street region between the first active region and the second active region. The wafer includes a first device formed on the substrate in the first active region. The first device includes a first portion of the channel layer. The wafer includes a second device formed on the substrate in the second active region. The second device includes a second portion of the channel layer. The wafer includes a conductive channel between the first active region and the second active region. The conductive channel is in the saw street of the wafer and includes a third portion of the channel layer.

What is claimed is: 
     
       1. A wafer, comprising:
 a substrate that includes a channel layer, a first active region, a second active region, and a saw street region between the first active region and the second active region; 
 a first device formed on the substrate in the first active region, wherein the first device includes a first portion of the channel layer; 
 a second device formed on the substrate in the second active region, wherein the second device includes a second portion of the channel layer; and 
 a conductive channel between the first active region and the second active region, wherein the conductive channel is in the saw street of the wafer and includes a third portion of the channel layer, wherein a dielectric layer is formed over the entire first portion, second portion, and third portion of the channel layer, and wherein a conductive via pad extends over the dielectric layer, connecting a back metal layer through a high resistivity region separating the first portion of the channel region and the second portion of the channel region. 
 
     
     
       2. The wafer of  claim 1 , wherein the conductive channel does not include a metal. 
     
     
       3. The wafer of  claim 1 , further comprising a barrier layer over the channel layer and wherein the conductive channel includes a two-dimensional electron gas along an interface between the channel layer and the barrier layer. 
     
     
       4. The wafer of  claim 1 , wherein the conductive channel extends around a perimeter of at least one of the first active region and the second active region. 
     
     
       5. The wafer of  claim 1 , further comprising a conductive ring over the substrate, wherein the conductive ring extends around a perimeter of the substrate and is electrically connected to the third portion of the channel layer. 
     
     
       6. The wafer of  claim 1 , wherein the third portion of the channel layer is electrically isolated from the first portion of the channel layer by a first high resistivity region of the wafer, and the third portion of the channel layer is electrically isolated from the second portion of the channel layer by a second high resistivity region of the wafer. 
     
     
       7. The wafer of  claim 1 , wherein the first device is a transistor having a current carrying electrode and the third portion of the channel layer is electrically connected to the current carrying electrode. 
     
     
       8. The wafer of  claim 7 , wherein the third portion of the channel layer extends underneath the current carrying electrode of the first device. 
     
     
       9. The wafer of  claim 7 , wherein the current carrying electrode is a source electrode of the transistor. 
     
     
       10. A device, comprising:
 a substrate that includes a channel layer; 
 a first active region formed on the substrate, wherein the first active region includes a first portion of the channel layer; 
 a second active region formed on the substrate, wherein the second active region includes a second portion of the channel layer; 
 a conductive channel between the first active region and the second active region, wherein the conductive channel includes a third portion of the channel layer, wherein the third portion of the channel layer is electrically isolated from the first portion of the channel layer in a planar region, and the third portion of the channel layer is electrically isolated from the second portion of the channel layer; and 
 a dielectric layer formed over the first portion, second portion, and third portion of the channel layer, wherein a conductive via pad extends over the dielectric layer, connecting a back metal layer through a high resistivity region separating the first portion of the channel region and the second portion of the channel region. 
 
     
     
       11. The device of  claim 10 , wherein the conductive channel includes a semiconducting material. 
     
     
       12. The device of  claim 11 , further comprising a barrier layer over the channel layer and wherein the conductive channel includes a two-dimensional electron gas along an interface between the channel layer and the barrier layer. 
     
     
       13. The device of  claim 10 , wherein the conductive channel extends around a perimeter of at least one of the first active region and the second active region. 
     
     
       14. The device of  claim 10 , further comprising a conductive ring on the substrate, wherein the conductive ring extends around at least a portion of a perimeter of the substrate and is electrically connected to the third portion of the channel layer.