Semiconductor device and method of fabricating the same

Abstract

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a substrate including an active pattern; 
 a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked to be spaced apart from each other; 
 a source/drain pattern connected to the plurality of semiconductor patterns; 
 a gate electrode on the plurality of semiconductor patterns, the gate electrode extending in a first direction that is parallel to a top surface of the substrate; and 
 a gate insulating layer between the plurality of semiconductor patterns and the gate electrode, 
 wherein a first semiconductor pattern of the plurality of semiconductor patterns includes opposite side surfaces, which are opposite to each other in the first direction, a bottom surface, and a top surface, 
 wherein the gate insulating layer covers the opposite side surfaces of the first semiconductor pattern, the bottom surface of the first semiconductor pattern, and the top surface of the first semiconductor pattern, 
 wherein the gate insulating layer includes
 a first region on one of the opposite side surfaces of the first semiconductor pattern; and 
 a second region on one of the top surface of the first semiconductor pattern or the bottom surface of the first semiconductor pattern, and 
 
 wherein a thickness of the first region in the first direction is greater than a thickness of the second region in a second direction that is perpendicular to the top surface of the substrate. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the gate insulating layer comprises:
 an interface layer which directly covers the first semiconductor pattern, and 
 a high-k dielectric layer which is on the interface layer. 
 
     
     
       3. The semiconductor device of  claim 2 , wherein a thickness in the first direction of the interface layer of the first region is greater than a thickness in the second direction of the interface layer of the second region. 
     
     
       4. The semiconductor device of  claim 2 , wherein a thickness in the first direction of the high-k dielectric layer of the first region is greater than a thickness in the second direction of the high-k dielectric layer of the second region. 
     
     
       5. The semiconductor device of  claim 2 , wherein
 the gate insulating layer further comprises an intermediate layer between the interface layer and the high-k dielectric layer, and 
 the intermediate layer is selectively on the first region such that the second region is exposed by the intermediate layer. 
 
     
     
       6. The semiconductor device of  claim 1 , wherein
 the one of the opposite side surfaces of the first semiconductor pattern comprises a first crystallographic plane that is normal to the first direction, and 
 the one of the top surface of the first semiconductor pattern or the bottom surface of the first semiconductor pattern comprises a second crystallographic plane that is normal to the second direction. 
 
     
     
       7. The semiconductor device of  claim 6 , wherein
 the first crystallographic plane is a {1 1 0} crystallographic plane, and 
 the second crystallographic plane is a {1 0 0} crystallographic plane. 
 
     
     
       8. The semiconductor device of  claim 1 , wherein
 the gate electrode comprises a portion that is between the first semiconductor pattern and a second semiconductor pattern of the plurality of semiconductor patterns, the second semiconductor pattern adjacent to the first semiconductor pattern, 
 the gate insulating layer comprises a third region between the portion of the gate electrode and the source/drain pattern and a fourth region between the portion of the gate electrode and the second semiconductor pattern, and 
 a thickness of the third region perpendicular to the second direction is greater than a thickness of the fourth region in the second direction. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the third region of the gate insulating layer directly covers a side surface of the source/drain pattern. 
     
     
       10. The semiconductor device of  claim 8 , wherein
 the source/drain pattern comprises a protruding portion protruding toward the portion of the gate electrode, and 
 a side surface of the source/drain pattern has a wavy profile such that a position of the side surface oscillates perpendicularly to the second direction as the side surface of the source/drain pattern extends in the second direction. 
 
     
     
       11. A semiconductor device, comprising:
 a substrate including an active pattern; 
 a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked to be spaced apart from each other; 
 a source/drain pattern connected to the plurality of semiconductor patterns; 
 a gate electrode on the plurality of semiconductor patterns; and 
 a gate insulating layer between the plurality of semiconductor patterns and the gate electrode, 
 wherein the gate electrode comprises a portion between a first semiconductor pattern and a second semiconductor pattern which are two adjacent semiconductor patterns of the plurality of semiconductor patterns, 
 wherein the gate insulating layer includes
 a first region between the portion of the gate electrode and a side surface of the source/drain pattern; and 
 a second region between the portion of the gate electrode and a bottom surface of the second semiconductor pattern, 
 
 wherein the first region of the gate insulating layer directly covers the side surface of the source/drain pattern, 
 wherein a thickness of the first region in a first direction that is parallel to a top surface of the substrate is greater than a thickness of the second region in a second direction that is perpendicular to the top surface of the substrate, and 
 wherein a central portion of the first region of the gate insulating layer is recessed towards the gate electrode in the first direction. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein
 the side surface of the source/drain pattern comprises a {1 1 0} crystallographic plane, and 
 the bottom surface of the second semiconductor pattern comprises a {1 0 0} crystallographic plane. 
 
     
     
       13. The semiconductor device of  claim 11 , wherein the gate insulating layer comprises
 an interface layer, which covers the side surface of the source/drain pattern and the bottom surface of the second semiconductor pattern, and 
 a high-k dielectric layer on the interface layer. 
 
     
     
       14. The semiconductor device of  claim 13 , wherein a thickness of the interface layer of the first region in the first direction is greater than a thickness of the interface layer of the second region in the second direction. 
     
     
       15. The semiconductor device of  claim 13 , wherein
 the gate insulating layer further comprises an intermediate layer between the interface layer and the high-k dielectric layer, and 
 the intermediate layer is selectively on the first region such that the second region is exposed by the intermediate layer. 
 
     
     
       16. A semiconductor device, comprising:
 a substrate including an active region; 
 a device isolation layer defining an active pattern on the active region; 
 a channel pattern and a source/drain pattern on the active pattern; 
 a gate electrode on the channel pattern, the gate electrode extending in a first direction that is parallel to a top surface of the substrate; 
 a gate insulating layer between the gate electrode and the channel pattern; 
 a gate spacer on a side surface of the gate electrode; 
 a gate capping pattern on a top surface of the gate electrode; 
 an interlayer insulating layer on the gate capping pattern; 
 an active contact that penetrates the interlayer insulating layer and is electrically connected to the source/drain pattern; 
 a metal-semiconductor compound layer between the active contact and the source/drain pattern; 
 a gate contact that penetrates the interlayer insulating layer and the gate capping pattern and is electrically connected to the gate electrode; 
 a first metal layer on the interlayer insulating layer, the first metal layer including first interconnection lines, which are electrically connected to the active contact and the gate contact, respectively, and a power line; and 
 a second metal layer on the first metal layer, 
 wherein the second metal layer includes second interconnection lines electrically connected to the first metal layer, 
 the channel pattern comprises a plurality of semiconductor patterns, which are stacked in a second direction perpendicular to the top surface of the substrate, 
 the gate insulating layer encloses a first semiconductor pattern of the plurality of semiconductor patterns, 
 the gate insulating layer enclosing the first semiconductor pattern has a first thickness in the first direction and a second thickness in the second direction, and 
 the first thickness is greater than the second thickness. 
 
     
     
       17. The semiconductor device of  claim 16 , wherein the gate insulating layer comprises
 an interface layer, which directly covers the first semiconductor pattern, and 
 a high-k dielectric layer, which is provided on the interface layer. 
 
     
     
       18. The semiconductor device of  claim 17 , wherein a thickness of the interface layer is greater in the first direction than in the second direction. 
     
     
       19. The semiconductor device of  claim 17 , wherein a thickness of the high-k dielectric layer is greater in the first direction than in the second direction. 
     
     
       20. The semiconductor device of  claim 17 , wherein
 the gate insulating layer further comprises an intermediate layer between the interface layer and the high-k dielectric layer, 
 the interface layer, the intermediate layer, and the high-k dielectric layer are stacked in the first direction, and 
 the intermediate layer is omitted from a region between the interface layer and the high-k dielectric layer stacked in the second direction, such that the interface layer and the high-k dielectric layer are in direct contact with each other in the second direction in the region.