Interconnect structure including topological material

Abstract

A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a substrate; and 
 an interconnect layer disposed over the substrate and including an interconnect structure, the interconnect structure including a topological material, 
 wherein 
 the interconnect structure includes a first conductive line and a second conductive line which are spaced apart from each other to form a trench between the first conductive line and the second conductive line and which include the topological material; 
 the interconnect layer further includes a first dielectric liner which is disposed in the trench and between the first conductive line and the second conductive line and which conformally covers a lateral wall of each of the first conductive line and the second conductive line, and a capping layer disposed in the trench; and 
 the first dielectric liner cooperates with the capping layer to define an air gap. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the topological material includes a topological insulator, a topological semimetal, or a combination thereof. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the interconnect structure further includes a magnetic material. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the interconnect structure further includes:
 a via contact disposed on a corresponding one of the first conductive line and the second conductive line, and 
 a conductive line disposed on and electrically connected to the via contact, 
 at least one of the via contact and the conductive line including the topological material. 
 
     
     
       5. The semiconductor device according to  claim 4 , wherein both the via contact and the conductive line include the topological material. 
     
     
       6. The semiconductor device according to  claim 5 , wherein the interconnect layer further includes a second dielectric liner laterally covering the via contact. 
     
     
       7. The semiconductor device according to  claim 1 , wherein each of the first conductive line and the second conductive line has an aspect ratio of height to width of greater than 1:1. 
     
     
       8. The semiconductor device according to  claim 1 , wherein each of the first conductive line and the second conductive line has an aspect ratio of height to width of less than 1:1. 
     
     
       9. A semiconductor device comprising:
 a substrate; 
 a first interconnect layer disposed over the substrate, and including a first interconnect structure containing a first topological material; and 
 a second interconnect layer disposed on the first interconnect layer, and including a second interconnect structure which includes a via contact disposed in an lower portion of the second interconnect layer and a first conductive line disposed in an upper portion of the second interconnect layer and electrically connected to the first interconnect structure through the via contact, at least one of the via contact and the first conductive line including a second topological material. 
 
     
     
       10. The semiconductor device according to  claim 9 , wherein each of the first topological material and the second topological material independently includes a topological insulator, a topological semimetal, or a combination thereof. 
     
     
       11. The semiconductor device according to  claim 9 , wherein both the via contact and the first conductive line include the second topological material. 
     
     
       12. The semiconductor device according to  claim 11 , wherein
 the first interconnect structure includes a first conductive line and a second conductive line which are spaced apart from each other to form a first trench between the first conductive line and the second conductive line of the first interconnect structure and one of which is electrically connected to the first conductive line of the second interconnect structure through the via contact; and 
 the first interconnect layer further includes a dielectric liner which is disposed in the first trench and between the first conductive line and the second conductive line of the first interconnect structure and which conformally covers a lateral wall of each of the first conductive line and the second conductive line of the first interconnect structure, and a capping layer disposed in the first trench. 
 
     
     
       13. The semiconductor device according to  claim 12 , wherein the dielectric liner cooperates with the capping layer to define an air gap. 
     
     
       14. The semiconductor device according to  claim 12 , wherein
 the second interconnect structure further includes a second conductive line which is spaced apart from the first conductive line of the second interconnect structure to form a second trench between the first conductive line and the second conductive line of the second interconnect structure; and 
 the second interconnect layer further includes
 a first dielectric liner laterally covering the via contact, 
 a second dielectric liner which is disposed in the second trench and between the first conductive line and the second conductive line of the second interconnect structure and which conformally covers a lateral wall of each of the first conductive line and the second conductive line of the second interconnect structure, and 
 a capping layer disposed in the second trench. 
 
 
     
     
       15. A semiconductor device comprising:
 a substrate; 
 a dielectric layer disposed over the substrate; and 
 an interconnect layer disposed on the dielectric layer, and including an interconnect structure and a dielectric liner in contact with the dielectric layer and laterally covering the interconnect structure, the interconnect structure including a topological material which includes a topological insulator, a topological semimetal, or a combination thereof, 
 wherein the interconnect layer further includes a capping layer cooperating with the dielectric liner to define an air gap. 
 
     
     
       16. The semiconductor device according to  claim 15 , wherein the topological insulator includes bismuth telluride, antimony telluride, bismuth-antimony alloy, bismuth selenide, or combinations thereof. 
     
     
       17. The semiconductor device according to  claim 15 , wherein the topological semimetal includes niobium phosphide, tantalum arsenide, niobium arsenide, tantalum phosphide, tungsten ditelluride, molybdenum ditelluride, tungsten diphosphide, molybdenum diphosphide, cadmium arsenide, platinum stannide, lanthanum antimonide, lanthanum bismuthide, platinum bismuthide), zirconium pentatelluride, hafnium pentatelluride, lead tantalum selenide, zirconium silicon sulfide, hafnium silicide sulfide, niobium arsenide, tantalum arsenide, or combinations thereof. 
     
     
       18. The semiconductor device according to  claim 15 , wherein the interconnect structure further includes a magnetic material, which includes cobalt, iron, nickel, or combinations thereof. 
     
     
       19. The semiconductor device according to  claim 15 , wherein the dielectric liner includes a base portion in contact with the dielectric layer, and a wall portion extending from the base portion and laterally covering the interconnect structure. 
     
     
       20. The semiconductor device according to  claim 19 , wherein the capping layer is in contact with an upper part of the wall portion of the dielectric liner.