Dynamic word line boosting during programming of a memory device

Abstract

The memory device includes a memory block, which includes a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry in communication with the memory block. The control circuitry is configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines. During the programming operation, the control circuitry is configured to apply a programming pulse VPGM to a selected word line to the selected word line, apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line, and apply a second pass voltage to a second set of word lines of the plurality of word. The first pass voltage is greater than the second pass voltage.

What is claimed is: 
     
         1 . A method of programming a memory device, comprising the steps of:
 preparing a memory block that includes a plurality of memory cells arranged in a plurality of word lines, the plurality of word lines being subdivided into a plurality of sub-blocks that can be erased independently of one another and are separated from one another by dummy word lines;   programming the memory cells of a selected word line of the plurality of word lines in a plurality of program loops, the selected word line being located in a selected sub-block of the plurality of sub-blocks, at least some program loops of the plurality of program loops including;
 applying a programming pulse VPGM to the selected word line, 
 applying a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line and including up to two already-programmed word lines on one side of the selected word line, 
 applying a second pass voltage to a second set of word lines of the plurality of word lines, 
 applying a third pass voltage to the word lines of an unselected sub-block of the plurality of sub-blocks, and 
 the first pass voltage being greater than the second pass voltage, and the second pass voltage being greater than the third pass voltage. 
   
     
     
         2 . The method of programming the memory device as set forth in  claim 1 , wherein the first set of word lines further includes a plurality of unprogrammed word lines on an opposite side of the selected word line from the up to two programmed word lines. 
     
     
         3 . The method of programming the memory device as set forth in  claim 1 , wherein upon completion of the programming operation of the selected word line, a word line of the plurality of word lines that is immediately adjacent the selected word line is designated as the new selected word line, and a programming operation begins on the new selected word line. 
     
     
         4 . The method of programming the memory device as set forth in  claim 1 , wherein the second set of word lines includes only programmed word lines. 
     
     
         5 . The method of programming the memory device as set forth in  claim 1 , wherein the memory block is programmed using a reverse order programming operation wherein programming proceeds on a word line by word line basis from a first word line on a drain side of the selected sub-block to a last word line on a source side of the selected sub-block. 
     
     
         6 . A memory device, comprising:
 a memory block that includes a plurality of memory cells arranged in a plurality of word lines, the plurality of word lines being sub-divide into a plurality of sub-blocks that can be erased independently of one another and that are separated from one another by dummy word lines;   control circuitry in communication with the memory block and being configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines, the selected word line being located in a selected sub-block of the plurality of sub-blocks, during the programming operation, the control circuitry being configured to;
 apply a programming pulse VPGM to the selected word line, 
 apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line and including up to two programmed word lines on one side of the selected word line, 
 apply a second pass voltage to a second set of word lines of the plurality of word, 
 apply a third pass voltage to all of the word lines of at least one unselected sub-block of the plurality of sub-blocks, and 
 wherein the first pass voltage is greater than the second pass voltage and the second pass voltage is greater than the third pass voltage. 
   
     
     
         7 . The memory device as set forth in  claim 6 , wherein the first set of word lines further includes a plurality of unprogrammed word lines on an opposite side of the selected word line from the up to two programmed word lines. 
     
     
         8 . The memory device as set forth in  claim 6 , wherein upon completion of the programming operation of the selected word line, the control circuitry designates a word line of the plurality of word lines that is immediately adjacent the selected word line as the new selected word line, and the control circuitry begins a programming operation on the new selected word line. 
     
     
         9 . The memory device as set forth in  claim 6 , wherein the second set of word lines includes only programmed word lines. 
     
     
         10 . The memory device as set forth in  claim 6 , wherein the control circuitry is configured to program the memory block using a reverse order programming operation wherein programming proceeds on a word line by word line basis from a first word line on a drain side of the selected sub-block to a last word line on a source side of the selected sub-block. 
     
     
         11 . An apparatus, comprising:
 a memory block that includes a plurality of memory cells arranged in a plurality of word lines, the plurality of word lines being divided into a plurality of sub-blocks that can be programmed and erased independently of one another and that are separated from one another by dummy word lines;   a programming means for programming the memory cells of the memory block, the programming means being in communication with the memory block and being configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines, during at least one program loop of the programming operation, the control circuitry being configured to;
 apply a programming pulse VPGM to the selected word line, 
 apply a first pass voltage VPASS  1  to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line and including up to two already-programmed word lines on one side of the selected word line, 
 apply a second pass voltage VPASS  2  to a second set of word lines of the plurality of word lines; 
 apply a third pass voltage VPASS_ 3  to a third set of word lines of the plurality of word, the third set of word lines including all of the word lines in an unselected sub-block of the plurality of sub-blocks, and 
 wherein the first pass voltage VPASS_ 1  is greater than the second pass voltage and the second pass voltage is greater than the third pass voltage VPASS_ 3 . 
   
     
     
         12 . The apparatus as set forth in  claim 11 , wherein the first set of word lines further includes a plurality of unprogrammed word lines on an opposite side of the selected word line from the up to two programmed word lines.