Microelectronic devices including ferroelectric capacitors with lower electrodes extending into contact holes and related methods

Abstract

A microelectronic device includes an insulating layer on a microelectronic substrate wherein the insulating layer has a contact hole therein exposing a portion of the microelectronic substrate. A first capacitor electrode is provided on a surface of the insulating layer opposite the microelectronic substrate and adjacent the contact hole wherein a lower portion of the first capacitor electrode extends into the contact hole below the surface of the insulating layer. A ferroelectric layer is provided on the first capacitor electrode, and a second capacitor electrode is provided on the ferroelectric layer. Related methods and memory devices are also discussed.

That which is claimed is:  
     
         1 . A microelectronic device comprising: 
 an insulating layer on a microelectronic substrate wherein said insulating layer has a contact hole therein exposing a portion of said microelectronic substrate;    a first capacitor electrode on a surface of said insulating layer opposite said microelectronic substrate and adjacent said contact hole wherein a lower portion of said first capacitor electrode extends into said contact hole below said surface of said insulating layer;    a ferroelectric layer on said first capacitor electrode opposite said insulating layer; and    a second capacitor electrode on said ferroelectric layer opposite said first capacitor electrode.    
     
     
         2 . A microelectronic device according to claim I wherein said first capacitor electrode extends through said contact hole to said exposed portion of said substrate.  
     
     
         3 . A microelectronic device according to claim I further comprising: 
 a recessed contact plug in said contact hole wherein said recessed contact plug provides electrical connection between said first capacitor electrode and said substrate.    
     
     
         4 . A microelectronic device according to    claim 3    further comprising a barrier layer between said first capacitor electrode and said recessed contact plug.  
     
     
         5 . A microelectronic device according to    claim 4    wherein said barrier layer comprises a material chosen from the group consisting of Ti, TiN, Ta, TaN, TiSiN, TiAlN, TaAlN, and WBN.  
     
     
         6 . A microelectronic device according to    claim 3    wherein an upper portion of said recessed contact plug opposite said substrate is in the range of 500 Angstroms to 1000 Angstroms below said surface of said insulating layer.  
     
     
         7 . A microelectronic device according to    claim 3    wherein said recessed contact plug comprises a material chosen from the group consisting of polysilicon, tungsten (W), tungsten nitride (WN), and tungsten silicide (WSi).  
     
     
         8 . A microelectronic device according to    claim 1    wherein said first capacitor electrode comprises a material chosen from the group consisting of Pt, Ir, Rh, Ru, Re, Os, and alloys and conductive oxides thereof.  
     
     
         9 . A microelectronic device according to    claim 1    wherein said first capacitor electrode has a thickness of at least approximately 1000 Angstroms.  
     
     
         10 . A microelectronic device according to    claim 1    wherein said first capacitor electrode extends across said surface of said insulating layer opposite said substrate.  
     
     
         11 . A microelectronic memory device comprising: 
 a semiconductor substrate;    a memory cell access transistor at a surface of said semiconductor substrate wherein said memory cell access transistor includes first and second spaced apart source/drain regions of said semiconductor substrate;    an insulating layer on said substrate and on said memory cell access transistor wherein said insulating layer has a contact hole therein exposing a portion of one of said source/drain regions;    a first capacitor electrode on a surface of said insulating layer opposite said microelectronic substrate and adjacent said contact hole wherein a lower portion of said first capacitor electrode extends into said contact hole below said surface of said insulating layer and wherein said first capacitor electrode is electrically coupled to said exposed portion of said source/drain region;    a ferroelectric layer on said first capacitor electrode opposite said insulating layer; and    a second capacitor electrode on said ferroelectric layer opposite said first capacitor electrode.    
     
     
         12 . A microelectronic memory device according to    claim 11    wherein said first capacitor electrode extends through said contact hole to said exposed portion of said source/drain region.  
     
     
         13 . A microelectronic memory device according to    claim 11    further comprising: 
 a recessed contact plug in said contact hole wherein said recessed contact plug provides electrical connection between said first capacitor electrode and said exposed portion of said source/drain region.  
 
     
     
         14 . A microelectronic memory device according to    claim 13    further comprising a barrier layer between said first capacitor electrode and said recessed contact plug.  
     
     
         15 . A microelectronic memory device according to    claim 14    wherein said barrier layer comprises a material chosen from the group consisting of Ti, TiN, Ta, TaN, TiSiN, TiAlN, TaAlN, and WBN.  
     
     
         16 . A microelectronic memory device according to    claim 13    wherein an upper portion of said recessed contact plug opposite said substrate is in the range of 500 Angstroms to 1000 Angstroms below said surface of said insulating layer.  
     
     
         17 . A microelectronic memory device according to    claim 13    wherein said recessed contact plug comprises a material chosen from the group consisting of polysilicon, tungsten (W), tungsten nitride (WN), and tungsten suicide (WSi).  
     
     
         18 . A microelectronic memory device according to    claim 11    wherein said first capacitor electrode comprises a material chosen from the group consisting of Pt, Ir, Rh, Ru, Re, Os, and alloys and conductive oxides thereof.  
     
     
         19 . A microelectronic memory device according to    claim 11    wherein said first capacitor electrode has a thickness of at least approximately 1000 Angstroms.  
     
     
         20 . A microelectronic memory device according to    claim 11    wherein said first capacitor electrode extends across said surface of said insulating layer opposite said substrate.  
     
     
         21 . A method for forming a microelectronic device, said method comprising the steps of: 
 forming an insulating layer on a microelectronic substrate wherein said insulating layer has a contact hole therein exposing a portion of said microelectronic substrate;    forming a first capacitor electrode on a surface of said insulating layer opposite said microelectronic substrate and adjacent said contact hole wherein a lower portion of said first capacitor electrode extends into said contact hole below said surface of said insulating layer;    forming a ferroelectric layer on said first capacitor electrode opposite said insulating layer; and    forming a second capacitor electrode on said ferroelectric layer opposite said first capacitor electrode.    
     
     
         22 . A method according to    claim 21    wherein said first capacitor electrode extends through said contact hole to said exposed portion of said substrate.  
     
     
         23 . A method according to    claim 21    wherein said step of forming said first capacitor electrode is preceded by the step of: 
 forming a recessed contact plug in said contact hole wherein said recessed contact plug provides electrical connection between said first capacitor electrode and said substrate.  
 
     
     
         24 . A method according to    claim 23    wherein said step of forming said recessed contact plug comprises the steps of: 
 forming a layer of a contact plug material on said insulating layer opposite said substrate wherein said contact plug material fills said contact hole; and  
 etching said layer of said contact plug material back to form said recessed contact plug.  
 
     
     
         25 . A method according to    claim 23    wherein said step of forming said first capacitor electrode comprises sputter depositing said first capacitor electrode.  
     
     
         26 . A method according to    claim 23    further comprising the step of: 
 forming a barrier layer between said first capacitor electrode and said recessed contact plug.  
 
     
     
         27 . A method according to    claim 26    wherein said barrier layer comprises a material chosen from the group consisting of Ti, TiN, Ta, TaN, TiSiN, TiAlN, TaAlN, and WBN.  
     
     
         28 . A method according to    claim 23    wherein an upper portion of said recessed contact plug opposite said substrate is in the range of 500 Angstroms to 1000 Angstroms below said surface of said insulating layer.  
     
     
         29 . A method according to    claim 23    wherein said recessed contact plug comprises a material chosen from the group consisting of polysilicon, tungsten (W), tungsten nitride (WN), and tungsten silicide (WSi).  
     
     
         30 . A method according to    claim 21    wherein said first capacitor electrode comprises a material chosen from the group consisting of Pt, Ir, Rh, Ru, Re, Os, and alloys and conductive oxides thereof.  
     
     
         31 . A method according to    claim 21    wherein said first capacitor electrode has a thickness of at least approximately 1000 Angstroms.  
     
     
         32 . A method according to    claim 21    wherein said first capacitor electrode extends across said surface of said insulating layer opposite said substrate.  
     
     
         33 . A method according to    claim 21    wherein said step of forming said first capacitor electrode comprises performing a chemical vapor deposition.  
     
     
         34 . A method for forming a microelectronic memory device, said method comprising the steps of: 
 forming a memory cell access transistor at a surface of a semiconductor substrate wherein said memory cell access transistor includes first and second spaced apart source/drain regions of said semiconductor substrate;    forming an insulating layer on said substrate and on said memory cell access transistor wherein said insulating layer has a contact hole therein exposing a portion of one of said source/drain regions;    forming a first capacitor electrode on a surface of said insulating layer opposite said microelectronic substrate and adjacent said contact hole wherein a lower portion of said first capacitor electrode extends into said contact hole below said surface of said insulating layer and wherein said first capacitor electrode is electrically coupled to said exposed portion of said source/drain region;    forming a ferroelectric layer on said first capacitor electrode opposite said insulating layer; and    forming a second capacitor electrode on said ferroelectric layer opposite said first capacitor electrode.    
     
     
         35 . A method according to    claim 34    wherein said first capacitor electrode extends through said contact hole to said exposed portion of said source/drain region.  
     
     
         36 . A method according to    claim 34    further comprising the step of: 
 forming a recessed contact plug in said contact hole wherein said recessed contact plug provides electrical connection between said first capacitor electrode and said exposed portion of said source/drain region.  
 
     
     
         37 . A method according to    claim 36    further comprising the step of: 
 forming a barrier layer between said first capacitor electrode and said recessed contact plug.  
 
     
     
         38 . A method according to    claim 37    wherein said barrier layer comprises a material chosen from the group consisting of Ti, TiN, Ta, TaN, TiSiN, TiAlN, TaAlN, and WBN.  
     
     
         39 . A method according to    claim 36    wherein an upper portion of said recessed contact plug opposite said substrate is in the range of 500 Angstroms to 1000 Angstroms below said surface of said insulating layer.  
     
     
         40 . A method according to    claim 36    wherein said recessed contact plug comprises a material chosen from the group consisting of polysilicon, tungsten (W), tungsten nitride (WN), and tungsten silicide (WSi).  
     
     
         41 . A method according to    claim 34    wherein said first capacitor electrode comprises a material chosen from the group consisting of Pt, Ir, Rh, Ru, Re, Os, and alloys and conductive oxides thereof.  
     
     
         42 . A method according to    claim 34    wherein said first capacitor electrode has a thickness of at least approximately 1000 Angstroms.  
     
     
         43 . A method according to    claim 34    wherein said first capacitor electrode extends across said surface of said insulating layer opposite said substrate.