Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip

Abstract

Semiconductor device having on a single substrate ( 1 ) at least one memory cell ( 3 ) and at least one logic transistor ( 25 ); the at least one memory cell having a floating gate ( 5 ), a tunnel oxide layer ( 11 ) between the floating gate and the substrate ( 1 ), a control gate ( 15 ), and a control oxide layer ( 13 ) between the control gate ( 15 ) and the floating gate ( 5 ); the at least one logic transistor ( 25 ) having a logic transistor gate ( 5′, 15″ ) and a logic transistor gate oxide ( 11″ ) between the logic transistor gate ( 5′, 15″ ) and the substrate ( 1 ), the tunnel oxide layer ( 11 ) of the memory cell ( 3 ) and the logic transistor gate oxide ( 11″ ) having a same or substantially same predetermined first thickness. The invention also relates to a method of manufacturing such a device and to such a device that also comprises a high voltage transistor ( 17 ) which is optionally made so as to be an integral part of at least the memory cell ( 3 ).

1 . Method of manufacturing on a single substrate ( 1 ) at least one memory cell ( 3 ) and at least one logic transistor ( 25 ); 
 the at least one memory cell comprising a floating gate ( 5 ), a tunnel oxide layer ( 11 ) between the floating gate and the substrate ( 1 ), a control gate ( 15 ;  6 ,  15 ), and a control oxide layer ( 13 ) between the control gate ( 15 ;  6 ,  15 ) and the floating gate ( 5 );    the at least one logic transistor ( 25 ) comprising a logic transistor gate ( 5 ′;  5 ′,  15 ″) and a logic transistor gate oxide ( 11 ″) between the logic transistor gate ( 5 ′,  5 ′,  15 ″) and the substrate ( 1 ),    characterized in that the tunnel oxide layer ( 11 ) of the memory cell ( 3 ) and the logic transistor gate oxide ( 11 ″) are made in a same step and have a same or substantially same predetermined first thickness.    
     
     
         2 . Method of manufacturing on a single substrate ( 1 ) at least one memory cell ( 3 ) and at least one high voltage transistor ( 17 ); 
 the at least one memory cell comprising a floating gate ( 5 ), a tunnel oxide layer ( 11 ) between the floating gate and the substrate ( 1 ), a control gate ( 15 ;  6 ,  15 ), and a control oxide layer ( 13 ) between the control gate ( 15 ;  6 ,  15 ) and the floating gate ( 5 );    the at least one high voltage transistor ( 17 ) comprising a high voltage transistor gate ( 15 ′;  5 ,  15 ′) and a high voltage transistor gate oxide ( 11 ′,  13 ′) between the high voltage transistor gate ( 15 ′;  6 ,  15 ′) and the substrate ( 1 ), characterized    in that high voltage transistor gate oxide ( 11 ′,  13 ′) comprises a first gate oxide layer ( 11 ′) on top of the substrate ( 1 ) and a second gate oxide layer ( 13 ′) on top of the first gate oxide layer ( 11 ′),    in that the first gate oxide layer ( 11 ′) and the tunnel oxide layer ( 11 ) of the memory cell are made in a same first step and have a same or substantially same predetermined first thickness,    and in that the second gate oxide layer ( 13 ′) and the control oxide layer ( 13 ) of the memory cell ( 3 ) are made in a same second step and have a same or substantially same predetermined second thickness.    
     
     
         3 . Method in accordance with    claim 2   , said method also including the manufacture of at least one logic transistor ( 25 ) on said substrate ( 1 ); 
 the at least one logic transistor ( 25 ) comprising a logic transistor gate ( 5 ′;  5 ′,  15 ″) and a logic transistor gate oxide ( 11 ″) between the logic transistor gate ( 5 ′,  5 ′,  15 ″) and the substrate ( 1 ), characterized in that the logic transistor gate oxide ( 11 ″) is also made in the same first step and has the same or substantially same predetermined first thickness.    
     
     
         4 . Method according to any one of the preceding claims, wherein said first thickness is between 2 and 10 nm.  
     
     
         5 . Method according to    claim 4   , wherein said first thickness is between 4 and 8 nm.  
     
     
         6 . Method according to any one of the preceding claims, wherein said floating gate ( 5 ) has a doping concentration of less than 1×10 20  cm −3 , preferably less than 4×10 19  cm −3 .  
     
     
         7 . Method according to any one of the preceding claims, wherein said logic gate transistor ( 25 ) comprises a first gate layer ( 5 ′) on top of said logic transistor gate oxide ( 11 ′) and a second gate layer ( 15 ″) on top of said first gate layer ( 5 ′).  
     
     
         8 . Method according to    claim 7   , wherein said first gate layer ( 5 ′) and said floating gate ( 5 ) are made simultaneously and have a same or substantially same predetermined third thickness and a same or substantially same predetermined doping concentration.  
     
     
         9 . Method according to    claim 3   , wherein said logic gate transistor ( 25 ) comprises a first gate layer ( 5 ′) on top of said logic transistor gate oxide ( 11 ′) and a second gate layer ( 15 ″) on top of said first gate layer ( 5 ′), said first gate layer ( 5 ′) and said floating gate ( 5 ) are made simultaneously and have a same or substantially same predetermined third thickness and a same or substantially same predetermined doping concentration, and said second gate layer ( 15 ″) and said high voltage transistor gate ( 15 ′) are made simultaneously and have a same or substantially same predetermined fourth thickness.  
     
     
         10 . Method according to    claim 9   , wherein said high voltage transistor gate comprises a first high voltage transistor gate layer ( 6 ′) on top of the high voltage transistor gate oxide ( 11 ′,  13 ′) and a second high voltage transistor gate layer ( 15 ′) on top of the first high voltage transistor gate layer ( 6 ′), the first high voltage transistor layer ( 6 ′) and the first gate layer ( 5 ′) being made simultaneously and having a same or substantially same predetermined fifth thickness.  
     
     
         11 . Method according to    claim 10   , wherein said control gate has a first control gate layer ( 6 ) on top of the control oxide layer ( 13 ) and a second control gate layer ( 15 ) on top of the first control gate layer ( 6 ), said first control gate layer ( 6 ) and the first gate layer ( 5 ′) being made simultaneously and having said same or substantially same predetermined fifth thickness.  
     
     
         12 . Semiconductor device comprising on a single substrate ( 1 ) at least one memory cell ( 3 ) and at least one logic transistor ( 25 ); 
 the at least one memory cell comprising a floating gate ( 5 ), a tunnel oxide layer ( 11 ) between the floating gate and the substrate ( 1 ), a control gate ( 15 ;  6 ,  15 ), and a control oxide layer ( 13 ) between the control gate ( 15 ;  6 ,  15 ) and the floating gate ( 5 );    the at least one logic transistor ( 25 ) comprising a logic transistor gate ( 5 ′;  5 ′,  15 ″) and a logic transistor gate oxide ( 11 ″) between the logic transistor gate ( 5 ′;  5 ′,  15 ″) and the substrate ( 1 ), characterized in that the tunnel oxide layer ( 11 ) of the memory cell ( 3 ) and the logic transistor gate oxide ( 11 ″) have a same or substantially same predetermined first thickness.    
     
     
         13 . Semiconductor device comprising on a single substrate ( 1 ) at least one memory cell ( 3 ) and at least one high voltage transistor ( 17 ); 
 the at least one memory cell comprising a floating gate ( 5 ), a tunnel oxide layer ( 11 ) between the floating gate and the substrate ( 1 ), a control gate ( 15 ;  6 ,  15 ), and a control oxide layer ( 13 ) between the control gate ( 15 ;  6 ,  15 ) and the floating gate ( 5 );    the at least one high voltage transistor ( 17 ) comprising a high voltage transistor gate ( 15 ′;  6 ′,  15 ′) and a high voltage transistor gate oxide ( 11 ′,  13 ′) between the high voltage transistor gate ( 15 ′;  6 ′,  15 ′) and the substrate ( 1 ), characterized    in that the high voltage transistor gate oxide ( 11 ′,  13 ′) comprises a first gate oxide layer ( 11 ′) on top of the substrate ( 1 ) and a second gate oxide layer ( 13 ′) on top of the first gate oxide layer ( 11 ′),    in that the first gate oxide layer ( 11 ′) and the tunnel oxide layer ( 11 ) of the memory cell have a same or substantially same predetermined first thickness,    and in that the second gate oxide layer ( 13 ′) and the control oxide layer ( 13 ) of the memory cell ( 3 ) have a same or substantially same predetermined second thickness.    
     
     
         14 . Semiconductor device according to    claim 13   , wherein said semiconductor device also includes at least one logic transistor ( 25 ) on said substrate ( 1 ); 
 the at least one logic transistor ( 25 ) comprising a logic transistor gate ( 5 ′;  5 ′,  15 ″) and a logic transistor gate oxide ( 11 ″) between the logic transistor gate ( 5 ′;  5 ′,  15 ″) and the substrate ( 1 ), characterized in that the logic transistor gate oxide ( 11 ″) also has the same or substantially same predetermined first thickness.    
     
     
         15 . Semiconductor device according to any one of the preceding claims  12 - 14 , wherein said first thickness is between 2 and 10 nm.  
     
     
         16 . Semiconductor device according to    claim 15   , wherein said first thickness is between 4 and 8 nm.  
     
     
         17 . Semiconductor device according to any one of the preceding claims  12 - 16 , wherein said floating gate ( 5 ) has a doping concentration of less than 1×10 20  cm −3 , preferably less than 4×10 19  cm −3 .  
     
     
         18 . Semiconductor device according to any one of the preceding claims  12 - 17 , wherein said logic gate transistor ( 25 ) comprises a first gate layer ( 5 ′) on top of said logic transistor gate oxide ( 11 ′) and a second gate layer ( 15 ″) on top of said first gate layer ( 5 ′).  
     
     
         19 . Semiconductor device according to    claim 18   , wherein said first gate layer ( 5 ′) and said floating gate ( 5 ) have a same or substantially same predetermined third thickness and a same or substantially same predetermined doping concentration.  
     
     
         20 . Semiconductor device according to    claim 14   , wherein said logic gate transistor ( 25 ) comprises a first gate layer ( 5 ′) on top of said logic transistor gate oxide ( 11 ′) and a second gate layer ( 15 ″) on top of said first gate layer ( 5 ′), said first gate layer ( 5 ′) and said floating gate ( 5 ) have a same or substantially same predetermined third thickness and a same or substantially same predetermined doping concentration, and said second gate layer ( 15 ″) and said high voltage transistor gate ( 15 ′) have a same or substantially same predetermined fourth thickness.  
     
     
         21 . Semiconductor device according to    claim 20   , wherein said high voltage transistor gate comprises a first high voltage transistor gate layer ( 6 ′) on top of the high voltage transistor gate oxide ( 11 ′,  13 ′) and a second high voltage transistor gate layer ( 15 ′) on top of the first high voltage transistor gate layer ( 6 ′), the first high voltage transistor layer ( 6 ′) and the first gate layer ( 5 ′) having a same or substantially same predetermined fifth thickness.  
     
     
         22 . Semiconductor device according to    claim 21   , wherein said control gate has a first control gate layer ( 6 ) on top of the control oxide layer ( 13 ) and a second control gate layer ( 15 ) on top of the first control gate layer ( 6 ), said first control gate layer ( 6 ) and the first gate layer ( 5 ′) having said same or substantially same predetermined fifth thickness.