Non-volatile memory structure and corresponding manufacturing process

Abstract

A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate. The floating gate is defined using only the mask and the Self-Aligned poly2/interpoly/poly1 stack etching. In one preferred method, a contact to the control gate is formed above the active area.

What is claimed is:  
     
         1 . A semiconductor non-volatile memory device comprising: 
 a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above the active area; and    a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors.    
     
     
         2 . The memory device as defined in    claim 1   , wherein the contact is substantially aligned with a central portion of the active area.  
     
     
         3 . The memory device as defined in    claim 1   , 
 wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and    the contact is located above the double-poly wings.    
     
     
         4 . The memory device as defined in    claim 1   , wherein the floating gate is defined by only a POLY2 mask and a Self-Aligned poly2/interpoly/poly1 stack etching.  
     
     
         5 . The memory device as defined in    claim 1   , wherein the device is a Flash-EEPROM.  
     
     
         6 . A semiconductor non-volatile memory device comprising: 
 a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above a field oxide region and not above the active area; and    a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors.    
     
     
         7 . A semiconductor non-volatile memory device comprising: 
 at least one memory cell including a floating gate transistor that has an active area, source and drain regions, a floating gate, and a control gate;    at least one selection transistor serially coupled to the floating gate transistor; and    a control gate line formed by at least a first metal interconnection layer, the control gate line being electrically connected to the control gate of the memory cell by a contact that is located above the active area.    
     
     
         8 . The memory device as defined in    claim 7   , wherein the contact is substantially aligned with a central portion of the active area.  
     
     
         9 . The memory device as defined in    claim 7   , 
 wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and    the contact is located above the double-poly wings.    
     
     
         10 . The memory device as defined in    claim 7   , further comprising a bit line formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region.  
     
     
         11 . The memory device as defined in    claim 10   , wherein the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to the first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.  
     
     
         12 . The memory device as defined in claim I  1 , wherein a metal layer island is provided around the other contact.  
     
     
         13 . An information handling system including at least one semiconductor nonvolatile memory device, said memory device comprising: 
 a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above the active area; and    a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors.    
     
     
         14 . The information handling system as defined in    claim 13   , wherein the contact is substantially aligned with a central portion of the active area.  
     
     
         15 . The information handling system as defined in    claim 13   , 
 wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and    the contact is located above the double-poly wings.    
     
     
         16 . A method for manufacturing a non-volatile memory device on a semiconductor substrate, the memory device including a plurality of memory cells arranged in a memory array, each of the memory cells having a floating gate transistor serially coupled to a selection transistor, the floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, said method comprising the steps of: 
 depositing a polyl layer;    depositing an interpoly dielectric layer above the poly1 layer;    depositing a poly2 layer above the interpoly dielectric layer;    providing a mask to define the control gate; and    using a Self-Aligned poly2/interpoly/poly1 stack etching to define a gate stack structure that includes the control gate and the floating gate,    wherein the floating gate is defined using only the mask and the Self-Aligned poly2/interpoly/poly1 stack etching.    
     
     
         17 . The method as defined in    claim 16   , further comprising the step of using another mask to remove selected portions of the interpoly dielectric layer before the step of depositing the poly2 layer.  
     
     
         18 . The method as defined in    claim 16   , further comprising the step of forming a contact to the control gate above the active area.  
     
     
         19 . The method as defined in    claim 18   , wherein the contact is substantially aligned with a central portion of the active area.  
     
     
         20 . The method as defined in    claim 16   , further comprising the step of: 
 forming a contact to the control gate,    wherein the floating gate and control gate are formed with double-poly wings that are asymmetric with respect to the active area, and    the contact is located above the double-poly wings.    
     
     
         21 . The method as defined in    claim 16   , further comprising the step of forming a contact to the control gate, the contact being located above a field oxide region and not above the active area.