Chip scale surface mount packages for semiconductor device

Abstract

A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board. The cap is then sawed along the scribe line with a saw whose kerf is small enough not to sever the contact between the metal layers. The dice are thereby completely detached from each other, forming individual semiconductor device packages.

We claim:  
     
         1 . A process of fabricating a semiconductor device package comprising: 
 providing a semiconductor wafer having a front side and a back side and comprising a plurality of dice separated by scribe lines, each die comprising a semiconductor device, a surface of a front side of a die comprising a passivation layer and at least one connection pad in electrical contact with the semiconductor device;    forming a first metal layer in electrical contact with the at least one connection pad, a portion of the first metal layer extending laterally beyond an edge of the die;    attaching a cap to the front side of the wafer;    cutting through the semiconductor wafer from the back side of the wafer in the scribe line area to form a first cut, the first cut having a first kerf W1 and exposing a part of the first metal layer;    forming a nonconductive layer on at least a portion of the back side of the die;    forming a second metal layer, the second metal layer being in electrical contact with the first metal layer and having a first section extending over the nonconductive layer; and    cutting through the cap in the scribe line area to form a second cut having a second kerf W2 that is less than the first kerf W1, the second cut leaving in place an area of contact between the first and second metal layers.    
     
     
         2 . The process of    claim 1    wherein the semiconductor device is a MOSFET and the front side of the die comprises a source connection pad and a gate connection pad, a source portion of the first metal layer being in contact with the source connection pad, a gate portion of the first metal layer being in contact with the gate connection pad, the source and gate portions of the first metal layer being electrically insulated from each other, the first section of the second metal layer being in contact with the source section of the first metal layer, the second metal layer comprising a second section in contact with the gate section of the first metal layer and a third section in contact with a drain terminal on the back side of the die, the first, second and third sections of the second metal layer being electrically insulated from each other.  
     
     
         3 . The process of    claim 1    wherein forming a first metal layer comprises sputtering a first metal sublayer and sputtering a second metal sublayer on the first metal sublayer.  
     
     
         4 . The process of    claim 3    wherein the first metal sublayer comprises titanium and the second metal sublayer comprises aluminum.  
     
     
         5 . The process of    claim 4    wherein forming a first metal layer comprises plating a third metal sublayer on the second metal sublayer.  
     
     
         6 . The process of    claim 5    wherein the third metal sublayer comprises nickel.  
     
     
         7 . The process of    claim 6    wherein forming a first metal layer comprises plating a fourth metal sublayer on the third metal sublayer.  
     
     
         8 . The process of    claim 7    wherein the fourth metal sublayer comprises gold.  
     
     
         9 . The process of    claim 1    wherein the cap is made of a material selected from the group consisting of glass, plastic, aluminum and copper.  
     
     
         10 . The process of    claim 1    wherein attaching a cap to the front side of the wafer comprises attaching the cap with a nonconductive adhesive.  
     
     
         11 . The process of    claim 1    further comprising thinning the semiconductor wafer after attaching a cap to the front side of the wafer.  
     
     
         12 . The process of    claim 11    wherein thinning the semiconductor wafer comprises grinding the back side of the wafer.  
     
     
         13 . The process of    claim 11    wherein thinning the semiconductor wafer comprises lapping the back side of the wafer.  
     
     
         14 . The process of    claim 11    wherein thinning the semiconductor wafer comprises etching the back side of the wafer.  
     
     
         15 . The process of    claim 11    wherein thinning the wafer comprises making the wafer as thin as is possible without damaging the internal microstructure of the semiconductor devices within the wafer.  
     
     
         16 . The process of    claim 1    wherein cutting through the semiconductor wafer from the back side of the wafer comprises cutting with a taper saw and etching.  
     
     
         17 . The process of    claim 1    wherein the first cut does not extend entirely through the first metal layer.  
     
     
         18 . The process of    claim 1    wherein forming a nonconductive layer on a back side of the die comprises: 
 depositing a layer of a nonconductive material;  
 depositing a mask layer on the layer of nonconductive material;  
 removing a portion of the mask layer to form openings in the mask layer, the openings overlying the second portion of the backside of the die and part of the first metal layer that was exposed by the first cut; and  
 etching the layer of nonconductive material through the openings in the mask layer.  
 
     
     
         19 . The process of    claim 1    wherein forming a nonconductive layer on a back side of the die comprises screen-printing.  
     
     
         20 . The process of    claim 1    wherein forming a second metal layer comprises sputtering a first metal sublayer and sputtering a second metal sublayer on the first metal sublayer.  
     
     
         21 . The process of    claim 20    wherein the first metal sublayer comprises titanium and the second metal sublayer comprises aluminum.  
     
     
         22 . The process of    claim 21    wherein forming a second metal layer comprises plating a third metal sublayer on the second metal sublayer.  
     
     
         23 . The process of    claim 22    wherein the third metal sublayer comprises nickel.  
     
     
         24 . The process of    claim 23    wherein forming a second metal layer comprises plating a fourth metal sublayer on the third metal sublayer.  
     
     
         25 . The process of    claim 24    wherein the fourth metal sublayer comprises gold.  
     
     
         26 . The process of    claim 1    further comprising forming at least one solder post on at least a part of the second metal layer.  
     
     
         27 . The process of    claim 1    further comprising forming at least one solder ball on at least a part of the second metal layer.  
     
     
         28 . The process of    claim 27    wherein forming at least one solder ball comprises screen-printing.  
     
     
         29 . The process of    claim 27    wherein forming at least one solder ball comprises solder jetting.  
     
     
         30 . The process of    claim 1    further comprising forming at least one conductive polymer ball on at least a part of the second metal layer.  
     
     
         31 . The process of    claim 1    wherein cutting through the cap comprises sawing.  
     
     
         32 . The process of    claim 1    wherein cutting through the cap comprises photolithographic patterning and etching.  
     
     
         33 . The process of    claim 1    further comprising cutting through the wafer and the cap in a direction perpendicular to the first and second cuts to separate the dice.  
     
     
         34 . The process of    claim 1    wherein the semiconductor device comprises a MOSFET.  
     
     
         35 . The process of    claim 1    wherein the semiconductor device comprises a diode.  
     
     
         36 . The process of    claim 1    wherein the semiconductor device comprises a JFET.  
     
     
         37 . The process of    claim 1    wherein the semiconductor device comprises a bipolar transistor.  
     
     
         38 . The process of    claim 1    wherein the semiconductor device comprises an IC.  
     
     
         39 . A process of fabricating a package for a power MOSFET comprising: 
 providing a semiconductor wafer having a front side and a back side and comprising a plurality of dice separated by scribe lines, each die comprising a power MOSFET, a surface of a front side of a die comprising a passivation layer, a gate connection pad and a source connection pad, a back side of the die comprising a drain terminal;    forming a front side gate metal layer in electrical contact with the gate connection pad, a portion of the front side gate metal layer extending laterally beyond an edge of the die;    forming a front side source metal layer in electrical contact with the source connection pad, a portion of the front side source metal layer extending laterally beyond the edge of the die, the front side gate and front side source metal layers being electrically insulated from each other;    attaching a cap to the front side of the wafer;    cutting through the semiconductor wafer from the back side of the wafer in the scribe line area to form a first cut, the first cut having a first kerf W1 and exposing a part of the front side gate and front side source metal layers;    forming a nonconductive layer on a portion of the back side of the die, the nonconductive layer leaving uncovered an exposed portion of the front side gate metal layer, an exposed portion of the front side source metal layer, and an exposed portion of a drain terminal of the MOSFET;    forming a back side gate metal layer, the back side gate metal layer extending over the nonconductive layer and electrically contacting the front side gate metal layer in a first area of contact;    forming a back side source metal layer, the back side source metal layer extending over the nonconductive layer and electrically contacting the front side source metal layer in a second area of contact;    forming a back side drain metal layer on the back side of the die in electrical contact with a drain terminal of the MOSFET;    cutting through the cap in the scribe line area to form a second cut having a second kerf W2 that is less than the first kerf W1, the second cut leaving in place the first and second areas of contact; and    cutting through the wafer and the cap in a direction perpendicular to the first and second cuts to separate the dice.    
     
     
         40 . The process of    claim 39    wherein the first cut does not extend entirely through the first and second metal layers  
     
     
         41 . A process for making an electrical connection between a first location on a first side of a semiconductor die and a second location on a second side of the semiconductor die, the process commencing while the die is a part of a semiconductor wafer, the process comprising: 
 forming a first metal layer extending laterally from the first location on the first side of the die to an area of the wafer beyond an edge of the die;    attaching a cap to the first side of the wafer;    cutting through the semiconductor wafer from the second side of the wafer to expose a part of the first metal layer;    forming a second metal layer extending laterally from the second location on the second side of the die and along an edge of the die to a region of contact with the first metal layer beyond the edge of the die; and    cutting through the cap while leaving intact the region of contact between the first and second metal layers.    
     
     
         42 . The process of    claim 41    comprising forming a nonconductive layer adjacent at least a portion of the second side of the die, wherein a portion of the second metal layer overlies the nonconductive layer.  
     
     
         43 . The process of    claim 41    wherein cutting through the semiconductor wafer comprises etching the semiconductor wafer to expose the part of the first metal layer.  
     
     
         44 . A package for a semiconductor device comprising: 
 a semiconductor die containing a semiconductor device, a front side of the die comprising at least one connection pad in electrical contact with at least one terminal of the semiconductor device;    a cap attached to the front side of the die;    a first metal layer in electrical contact with the connection pad, a first portion of the first metal layer being located between the die and the cap and a second portion of the first metal layer extending laterally beyond an edge of the die; and    a nonconductive layer adjacent a portion of the back side of the die; and    a second metal layer comprising a first section, the first section of the second metal layer being in electrical contact with the second portion of the first metal layer at a location beyond the edge of the die and extending around the edge of the die to a location adjacent the nonconductive layer on the back side of the die.    
     
     
         45 . The package of    claim 44    wherein the die is as thin as possible without damaging the internal microstructure of the semiconductor device.  
     
     
         46 . The package of    claim 44    wherein the first section of the second metal layer includes a slanted portion adjacent the edge of the die.  
     
     
         47 . The package of    claim 44    wherein the first metal layer includes a plurality of sublayers.  
     
     
         48 . The package of    claim 44    wherein the first metal layer includes at least one sputtered sublayer.  
     
     
         49 . The package of    claim 44    wherein the first metal layer includes at least one plated sublayer.  
     
     
         50 . The package of    claim 44    wherein the second metal layer includes a plurality of sublayers.  
     
     
         51 . The package of    claim 44    wherein the second metal layer includes at least one sputtered sublayer.  
     
     
         52 . The package of    claim 44    wherein the second metal layer includes at least one plated sublayer.  
     
     
         53 . The package of    claim 44    wherein the second metal layer includes a second section in electrical contact with a second terminal of the semiconductor device on the backside of the die, the second section of the second metal layer being electrically insulated from the first section of the second metal layer.  
     
     
         54 . The package of    claim 44    comprising at least a first solder post in contact with the first section of the second metal layer and at least a second solder post in contact with the second section of the second metal layer.  
     
     
         55 . The package of    claim 44    comprising at least a first solder ball in contact with the first section of the second metal layer and at least a second solder ball in contact with the second section of the second metal layer.  
     
     
         56 . The package of    claim 44    comprising at least a first conductive polymer ball in contact with the first metal layer and at least a second conductive polymer ball in contact with the second metal layer.  
     
     
         57 . The package of    claim 44    wherein an edge of the cap extends laterally beyond an edge of the die.  
     
     
         58 . The package of    claim 44    wherein the cap has a width X1 and the die has a width X2, X1 being greater than X2.  
     
     
         59 . The package of    claim 44    wherein the die comprises a vertical power MOSFET.  
     
     
         60 . The package of    claim 44    wherein the die comprises a diode.  
     
     
         61 . The package of    claim 44    wherein the die comprises a bipolar transistor.  
     
     
         62 . The package of    claim 44    wherein the die comprises a JFET.  
     
     
         63 . The package of    claim 44    wherein the die comprises a IC.  
     
     
         64 . A package for a MOSFET comprising: 
 a semiconductor die containing a MOSFET and having a width X2, a front side of the die comprising a source connection pad in electrical contact with a source terminal and a gate connection pad in electrical contact with a gate terminal, a back side of the die comprising a drain terminal;    a cap having a width X1 greater than X2 and being attached to the front side of the die;    a first source metal layer in electrical contact with the source connection pad, a first portion of the first source metal layer being located between the die and the cap and a second portion of the first source metal layer extending laterally beyond an edge of the die;    a first gate metal layer in electrical contact with the gate connection pad, a first portion of the first gate metal layer being located between the die and the cap and a second portion of the first gate metal layer extending laterally beyond an edge of the die;    a nonconductive layer adjacent a portion of the back side of the die; and    a second source metal layer in electrical contact with the second portion of the first source metal layer at a location beyond the edge of the die and extending around the edge of the die to a location adjacent the nonconductive layer on the back side of the die;    a second gate metal layer in electrical contact with the second portion of the first gate metal layer at a location beyond the edge of the die and extending around the edge of the die to a location adjacent the nonconductive layer on the back side of the die, the first and second source metal layers being electrically insulated from the first and second gate metal layers; and    a drain metal layer on the back side of the die in electrical contact with the drain terminal.    
     
     
         65 . The package of    claim 64    further comprising at least one solder post in contact with the second source metal layer, at least one solder post in contact with the second gate metal layer, and at least one solder post in contact with the drain metal layer.  
     
     
         66 . The package of    claim 64    further comprising at least one solder ball in contact with the second source metal layer, at least one solder ball in contact with the second gate metal layer, and at least one solder ball in contact with the drain metal layer.  
     
     
         67 . The package of    claim 64    further comprising at least one conductive polymer ball in contact with the second source metal layer, at least one conductive polymer ball in contact with the second gate metal layer, and at least one conductive polymer ball in contact with the drain metal layer.  
     
     
         68 . A package for a semiconductor device comprising: 
 a semiconductor die containing a semiconductor device, a first side of the die comprising a connection pad;    a cap attached to the first side of the die;    a first metal layer in electrical contact with the connection pad, the first metal layer extending laterally and terminating in a first flange beyond an edge of the die; and    a second metal layer extending from a second side of the die and along an edge of the die and terminating in a second flange beyond the edge of the die, the second flange being in contact with the first flange.    
     
     
         69 . The package of    claim 68    wherein an edge of the cap extends laterally beyond an edge of the die  
     
     
         70 . The package of    claim 68    wherein the first and second flanges extend longitudinally outward from die in a direction parallel to the sides of die.