Inventor · disambiguated record
Yueh-Se Ho
Also filed as: HO YUEH S · HO YUEH-SE
110 granted patents·14 pending applications·2,384 citations·filing 1986–2025
99Inventor score
Top patents by PatentIndex Score
124 records- 0196US6562647B2Chip scale surface mount package for semiconductor device and process of fabricating the sameVISHAY INTERTECHNOLOGY INC·Filed 2001·Granted May 13, 2003·130 cites·37 claims
- 0296US6392290B1Vertical structure for semiconductor wafer-level chip scale packagesSILICONIX INC·Filed 2000·Granted May 21, 2002·171 cites·23 claims
- 0396US5757081ASurface mount and flip chip technology for total integrated circuit isolationSILICONIX INC·Filed 1996·Granted May 26, 1998·224 cites·8 claims
- 0496US5639676ATrenched DMOS transistor fabrication having thick termination region oxideSILICONIX INC·Filed 1996·Granted Jun 17, 1997·138 cites·6 claims
- 0595US8513784B2Multi-layer lead frame package and method of fabricationLU JUN·Filed 2010·Granted Aug 20, 2013·24 cites·17 claims
- 0695US5753529ASurface mount and flip chip technology for total integrated circuit isolationSILICONIX INC·Filed 1995·Granted May 19, 1998·183 cites·7 claims
- 0795US5578851ATrenched DMOS transistor having thick field oxide in termination regionSILICONIX INC·Filed 1996·Granted Nov 26, 1996·136 cites·5 claims
- 0894US8642385B2Wafer level package structure and the fabrication method thereofXUE YAN XUN·Filed 2011·Granted Feb 4, 2014·22 cites·29 claims
- 0994US8581376B2Stacked dual chip package and method of fabricationYILMAZ HAMZA·Filed 2010·Granted Nov 12, 2013·22 cites·23 claims
- 1094US5767578ASurface mount and flip chip technology with diamond film passivation for total integated circuit isolationSILICONIX INC·Filed 1996·Granted Jun 16, 1998·176 cites·19 claims
- 1193US6249041B1IC chip package with directly connected leadsSILICONIX INC·Filed 1998·Granted Jun 19, 2001·196 cites·13 claims
- 1293US5316959ATrenched DMOS transistor fabrication using six masksSILICONIX INC·Filed 1992·Granted May 31, 1994·117 cites·8 claims
- 1392US8778735B1Packaging method of molded wafer level chip scale package (WLCSP)XUE YAN XUN·Filed 2013·Granted Jul 15, 2014·14 cites·10 claims
- 1491US8436429B2Stacked power semiconductor device using dual lead frame and manufacturing methodXUE YAN XUN·Filed 2011·Granted May 7, 2013·13 cites·10 claims
- 1591US7211877B1Chip scale surface mount package for semiconductor device and process of fabricating the sameVISHAY SILICONIX·Filed 2005·Granted May 1, 2007·19 cites·6 claims
- 1691US5468982ATrenched DMOS transistor with channel block at cell trench cornersSILICONIX INC·Filed 1994·Granted Nov 21, 1995·89 cites·21 claims
- 1790US9397029B1Power semiconductor package device having locking mechanism, and preparation method thereofALPHA & OMEGA SEMICONDUCTOR·Filed 2015·Granted Jul 19, 2016·7 cites·6 claims
- 1890US8952509B1Stacked multi-chip bottom source semiconductor device and preparation method thereofYILMAZ HAMZA·Filed 2013·Granted Feb 10, 2015·15 cites·15 claims
- 1990US8564110B2Power device with bottom source electrodeXUE YAN XUN·Filed 2012·Granted Oct 22, 2013·12 cites·16 claims
- 2089US9184117B2Stacked dual-chip packaging structure and preparation method thereofHO YUEH-SE·Filed 2012·Granted Nov 10, 2015·11 cites·18 claims
- 2189US8481368B2Semiconductor package of a flipped MOSFET and its manufacturing methodXUE YAN XUN·Filed 2011·Granted Jul 9, 2013·11 cites·5 claims
- 2289US8124453B2Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminatesSUN MING·Filed 2010·Granted Feb 28, 2012·10 cites·4 claims
- 2388US11101137B1Method of making reverse conducting insulated gate bipolar transistorALPHA & OMEGA SEMICONDUCTOR INT LP·Filed 2020·Granted Aug 24, 2021·2 cites·15 claims
- 2487US8981464B2Wafer level chip scale package and process of manufactureALPHA & OMEGA SEMICONDUCTOR·Filed 2014·Granted Mar 17, 2015·6 cites·9 claims
- 2587US7829989B2Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backsideALPHA & OMEGA SEMICONDUCTOR·Filed 2005·Granted Nov 9, 2010·14 cites·23 claims
- 2687US7208818B2Power semiconductor packageALPHA & OMEGA SEMICONDUCTOR·Filed 2004·Granted Apr 24, 2007·47 cites·15 claims
- 2787US6316287B1Chip scale surface mount packages for semiconductor device and process of fabricating the sameVISHAY INTERTECHNOLOGY INC·Filed 1999·Granted Nov 13, 2001·90 cites·43 claims
- 2886US7955893B2Wafer level chip scale package and process of manufactureALPHA & OMEGA SEMICONDUCTOR·Filed 2008·Granted Jun 7, 2011·11 cites·18 claims
- 2986US6876061B2Chip scale surface mount package for semiconductor device and process of fabricating the sameVISHAY INTERTECHNOLOGY INC·Filed 2002·Granted Apr 5, 2005·37 cites·22 claims
- 3086US6271060B1Process of fabricating a chip scale surface mount package for semiconductor deviceVISHAY INTERTECHNOLOGY INC·Filed 1999·Granted Aug 7, 2001·74 cites·35 claims
- 3185US10038106B2Termination structure for gallium nitride Schottky diodeALPHA & OMEGA SEMICONDUCTOR·Filed 2017·Granted Jul 31, 2018·2 cites·10 claims
- 3285US8563361B2Packaging method of molded wafer level chip scale package (WLCSP)XUE YAN XUN·Filed 2012·Granted Oct 22, 2013·8 cites·8 claims
- 3385US6744124B1Semiconductor die package including cup-shaped leadframeSILICONIX INC·Filed 1999·Granted Jun 1, 2004·75 cites·9 claims
- 3484US9269699B2Embedded package and method thereofALPHA & OMEGA SEMICONDUCTOR·Filed 2014·Granted Feb 23, 2016·6 cites·18 claims
- 3584US6841852B2Integrated circuit package for semiconductor devices with improved electric resistance and inductanceFiled 2002·Granted Jan 11, 2005·37 cites·7 claims
- 3683US9214417B2Combined packaged power semiconductor deviceHO YUEH-SE·Filed 2014·Granted Dec 15, 2015·5 cites·6 claims
- 3782US9478646B2Methods for fabricating anode shorted field stop insulated gate bipolar transistorBHALLA ANUP·Filed 2011·Granted Oct 25, 2016·4 cites·9 claims
- 3882US9406661B2Protection circuit including vertical gallium nitride schottky diode and PN junction diodeALPHA & OMEGA SEMICONDUCTOR·Filed 2015·Granted Aug 2, 2016·2 cites·6 claims
- 3982US8053891B2Standing chip scale packageALPHA & OMEGA SEMICONDUCTOR·Filed 2008·Granted Nov 8, 2011·8 cites·40 claims
- 4081US8987878B2Substrateless power device packagesFENG TAO·Filed 2010·Granted Mar 24, 2015·5 cites·7 claims
- 4181US8586414B2Top exposed package and assembly methodXUE YAN XUN·Filed 2010·Granted Nov 19, 2013·6 cites·17 claims
- 4281US8362606B2Wafer level chip scale packageALPHA & OMEGA SEMICONDUCTOR·Filed 2010·Granted Jan 29, 2013·5 cites·26 claims
- 4380US8716069B2Semiconductor device employing aluminum alloy lead-frame with anodized aluminumXUE YAN XUN·Filed 2012·Granted May 6, 2014·5 cites·9 claims
- 4480US8169062B2Integrated circuit package for semiconductior devices with improved electric resistance and inductanceLUO LEESHAWN·Filed 2011·Granted May 1, 2012·6 cites·20 claims
- 4580US7811904B2Method of fabricating a semiconductor device employing electroless platingALPHA & OMEGA SEMICONDUCTOR·Filed 2007·Granted Oct 12, 2010·7 cites·9 claims
- 4680US7183616B2High speed switching MOSFETS using multi-parallel die packages with/without special leadframesALPHA & OMEGA SEMICONDUCTOR·Filed 2002·Granted Feb 27, 2007·29 cites·22 claims
- 4780US6441475B2Chip scale surface mount package for semiconductor device and process of fabricating the sameVISHAY INTERTECHNOLOGY INC·Filed 2000·Granted Aug 27, 2002·26 cites·26 claims
- 4878US9171788B1Semiconductor package with small gate clip and assembly methodALPHA & OMEGA SEMICONDUCTOR·Filed 2014·Granted Oct 27, 2015·3 cites·12 claims
- 4978US8686546B2Combined packaged power semiconductor deviceHO YUEH-SE·Filed 2011·Granted Apr 1, 2014·5 cites·23 claims
- 5077US8067822B2Integrated circuit package for semiconductor devices with improved electric resistance and inductanceLUO LEESHAWN·Filed 2008·Granted Nov 29, 2011·7 cites·8 claims
Showing the top 50 of 124 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →