Method of fabricating field effect transistor

Abstract

A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

What is claimed is:  
     
         1 . A method of fabricating a field effect transistor, comprising steps of: 
 providing a substrate comprising a gate thereon, wherein the gate includes a dielectric layer on the substrate and an electrode on the dielectric layer;    forming a liner oxide layer adjacent to and covering a sidewall of the gate;    forming a first spacer adjacent to the liner oxide layer;    forming an epitaxial silicon layer aside of the first spacer on the substrate;    forming a shallow source/drain (S/D) extension junction in the substrate below the epitaxial silicon layer;    forming a second spacer covering the first spacer;    forming a S/D region aside of the second spacer in the substrate below the epitaxial silicon layer; and    transforming a part of the epitaxial silicon layer into a metal silicide layer.    
     
     
         2 . The fabricating method of    claim 1   , wherein the method of forming the epitaxial silicon layer includes chemical vapor deposition (CVD).  
     
     
         3 . The fabricating method of    claim 1   , wherein the epitaxial silicon layer includes SiGe.  
     
     
         4 . The fabricating method of    claim 1   , wherein the method of forming the shallow S/D extension junction includes implantation of ions whose conductivity is different from that of the substrate.  
     
     
         5 . The fabricating method of    claim 1   , wherein the first spacer includes a nitride layer.  
     
     
         6 . The fabricating method of    claim 1   , wherein the thickness of the liner oxide layer is about 50-200 Å.  
     
     
         7 . The fabricating method of    claim 1   , wherein the thickness of the first spacer is about 50-200 Å.  
     
     
         8 . The fabricating method of    claim 1   , wherein the method of forming the liner oxide layer and the first spacer includes anisotropic etching.  
     
     
         9 . The fabricating method of    claim 1   , wherein the thickness of the oxide layer is about 50-300 Å.  
     
     
         10 . The fabricating method of    claim 1   , wherein the thickness of the second spacer is about 200-1500 Å.  
     
     
         11 . The fabricating method of    claim 1   , wherein the method of transforming the epitaxial silicon layer into the metal silicide layer includes: 
 forming a metal layer to cover the epitaxial silicon layer;    performing a high temperature thermal process to produce a nitridation reaction between the metal layer and the epitaxial silicon layer; and    removing the remaining metal layer.    
     
     
         12 . A method of fabricating a metal silicide, comprising steps of: 
 providing a substrate;    forming an epitaxial silicon layer on the substrate;    forming a shallow S/D extension junction in the substrate below the epitaxial silicon layer;    forming a S/D region in the substrate below the epitaxial silicon layer; and    transforming a part of the epitaxial silicon layer into a metal silicide layer.    
     
     
         13 . The fabricating method of    claim 12   , wherein the method of forming the epitaxial silicon layer includes chemical vapor deposition (CVD).  
     
     
         14 . The fabricating method of    claim 12   , wherein the method of forming the shallow S/D extension junction includes implantation of ions whose conductivity is different from that of the substrate.  
     
     
         15 . The fabricating method of    claim 12   , wherein the method of transforming the epitaxial silicon layer into the metal silicide layer includes: 
 forming a metal layer to cover the epitaxial silicon layer;    performing a high temperature thermal process to produce a nitridation reaction between the metal layer and the epitaxial silicon layer; and    removing the remaining metal layer.    
     
     
         16 . A method of fabricating a field effect transistor, comprising steps of: 
 providing a substrate comprising a gate thereon;    forming a liner oxide layer on a sidewall of the gate;    forming a first spacer on the liner oxide layer;    forming an epitaxial silicon layer on the substrate aside of the first spacer;    performing a first ion implantation on the substrate with the gate and the first spacer as a mask;    forming a second spacer covering the first spacer;    performing a second ion implantation on the substrate with the first spacer, the second spacer and the gate as a mask;    forming a metal layer over the substrate; and    transforming the metal layer and at least a part of the epitaxial silicon layer into a metal silicide layer.    
     
     
         17 . The fabricating method of    claim 16   , wherein the first ion implantation step is performed with an ion concentration lighter than an ion concentration of the second ion implantation step.