Apparatus for improving alignment for metal masking

Abstract

A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.

1 . A semiconductor wafer polishing method comprising: 
 forming at least one alignment mark within an alignment area on a semiconductor wafer;    forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area; and    a polishing the layer.    
     
     
         2 . The semiconductor wafer polishing method of    claim 1    wherein the alignment mark comprises a tungsten metal filled trench.  
     
     
         3 . The semiconductor wafer polishing method of    claim 1    wherein the alignment mark comprises an elongate metal filled via.  
     
     
         4 . The semiconductor wafer polishing method of    claim 1    further comprising a raised structure provided within the layer to be polished, the raised structure provided about the alignment mark and extending elevationally from a surface from which the alignment mark extends.  
     
     
         5 . The semiconductor wafer polishing method of    claim 1    wherein the step of polishing the layer comprises chemical mechanical polishing.  
     
     
         6 . A semiconductor wafer polishing method comprising: 
 forming at least one alignment mark within an alignment area on a surface of a semiconductor wafer;    forming a structure about the alignment mark and extending elevationally from the surface from which the alignment mark extends;    forming a layer to be polished over the structure, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area; and    polishing the layer.    
     
     
         7 . The semiconductor wafer polishing method of    claim 6    wherein the step of forming at least one alignment mark comprises the step of forming a plurality of alignment marks in the form of an alignment target.  
     
     
         8 . The semiconductor wafer polishing method of    claim 6    wherein the structure comprises a circumferentially extending frame encircling the alignment mark.  
     
     
         9 . The semiconductor wafer polishing method of    claim 6    wherein the structure comprises a series of raised structures provided in adjacent spaced-apart relation about the alignment mark and extending elevationally from a lowermost portion of the alignment mark.  
     
     
         10 . The semiconductor wafer polishing method of    claim 6    further comprising the step of forming a contrasting metal layer on the layer to be polished.  
     
     
         11 . The semiconductor wafer polishing method of    claim 6    wherein the step of forming at least one alignment mark comprises providing an alignment trench within the layer to be polished and filling the alignment trench with metal.  
     
     
         12 . A semiconductor wafer polishing method comprising: 
 forming at least one alignment mark within an alignment area on a semiconductor wafer;    forming a series of raised structures in adjacent spaced-apart relation about the alignment mark and extending elevationally from a lowermost portion of the alignment mark;    forming a layer to be polished over the raised structures, the layer being formed to be generally elevationally higher about the alignment area than within the alignment area; and    polishing the layer.    
     
     
         13 . The semiconductor wafer polishing method of    claim 12    wherein the series of raised structures comprises a plurality of neighboring adjacent frame segments.  
     
     
         14 . The semiconductor wafer polishing method of    claim 13    wherein each frame segment comprises a rectangular element, and adjacent alternating rectangular elements are arranged with perpendicular major axes.  
     
     
         15 . The semiconductor wafer polishing method of    claim 12    wherein the raised structures comprise an array of neighboring frame segments encircling the alignment mark.  
     
     
         16 . The semiconductor wafer polishing method of    claim 12    wherein the step of forming a series of raised structures comprises depositing metal on the wafer.  
     
     
         17 . The semiconductor wafer polishing method of    claim 12    further comprising the step of using the alignment target to step and repeat a pattern on the wafer.  
     
     
         18 . A semiconductor wafer polishing method comprising: 
 preparing a semiconductor substrate having a surface including an alignment marking area;    depositing a raised portion on the surface to encompass the alignment marking area;    depositing a removable layer over the wafer including over the raised portion and the alignment marking area;    providing alignment trenches within the removable layer and within the alignment marking area to form alignment trenches;    depositing a contrasting layer on the removable layer and within the alignment trenches; and    chemical-mechanical polishing to remove the contrasting layer deposited over the removable layer and expose alignment marks comprising the contrasting layer deposited within the alignment trenches.    
     
     
         19 . The semiconductor wafer polishing method of    claim 18    wherein the step of providing alignment trenches within the removable layer comprises the step of etching alignment trenches within a portion of the removable layer within the alignment marking area.  
     
     
         20 . The semiconductor wafer polishing method of    claim 18    wherein the step of providing alignment trenches within the removable layer comprises the step of forming the removable layer so as to have elongate alignment trenches.  
     
     
         21 . The semiconductor wafer polishing method of    claim 18    wherein the removable layer comprises an electrically insulative material and the contrasting layer comprises an electrically conductive material.  
     
     
         22 . The semiconductor wafer polishing method of    claim 18    wherein the removable layer comprises an oxide layer and the contrasting layer comprises tungsten metal.  
     
     
         23 . The semiconductor wafer polishing method of    claim 18    wherein the raised portion comprises a continuous annular frame of topography encircling the alignment mark and underlying the removable layer.  
     
     
         24 . The semiconductor wafer polishing method of    claim 18    wherein the raised portion comprises a plurality of adjacent frame segments of topography encircling the alignment mark and underlying the removable layer.  
     
     
         25 . A method for improving alignment for metal masking with an oxide and tungsten chemical-mechanical polishing planarization process comprising the following steps: 
 preparing a semiconductor substrate having a surface including an alignment marking area;    depositing a raised portion on the surface to encompass the alignment marking area;    depositing a removable oxide layer over the wafer including over the raised portion and the alignment marking area;    forming alignment trenches in a portion of the removable layer within the alignment marking area;    depositing a contrasting tungsten layer on the removable layer and within the alignment trenches; and    chemical-mechanical polishing to remove the contrasting layer deposited over the removable layer and expose alignment marks comprising the tungsten layer deposited within the alignment trenches of the oxide layer.    
     
     
         26 . The method of    claim 25    wherein the raised portion comprises a circumferentially continuous raised annular portion extending entirely around the alignment marking area.  
     
     
         27 . The method of    claim 25    wherein the raised portion comprises a plurality of elongated raised portions encompassing the alignment marking area.  
     
     
         28 . The method of    claim 25    wherein the step of forming alignment trenches in a portion of the removable layer comprises removing a portion of the removable layer to form alignment trenches.  
     
     
         29 . The method of    claim 25    wherein the step of forming alignment trenches in a portion of the removable layer comprises depositing the removable oxide layer to form alignment trenches.  
     
     
         30 . The method of    claim 25    wherein the raised portion comprises a discontinuous frame encompassing the alignment marking area.  
     
     
         31 . A semiconductor wafer, comprising; 
 an alignment marking area formed relative to a surface of the wafer;    at least one alignment mark provided within the alignment area;    a structure formed about the alignment marking area and extending from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends; and    a layer of material to be polished provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.    
     
     
         32 . The semiconductor wafer of    claim 31    wherein the structure comprises a raised portion provided proximately about and surrounding the alignment marking area.  
     
     
         33 . The semiconductor wafer of    claim 31    wherein the structure comprises a series of raised structures provided proximately and in adjacent spaced-apart relation about the alignment marking area.  
     
     
         34 . The semiconductor wafer of    claim 31    wherein the alignment mark comprises an alignment target including a plurality of alignment marks.