Beol decoupling capacitor

Abstract

An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Having thus described our invention in detail, what we claims as new, and desire to secure by the letters patent is:  
     
         1 . A capacitor comprising an amorphous dielectric material having a dielectric constant of 10 or greater positioned between two electrodes.  
     
     
         2 . The capacitor of    claim 1    wherein the amorphous dielectric material is fabricated at temperatures below 450° C.  
     
     
         3 . The capacitor of    claim 1    wherein the amorphous dielectric constant material is a thin film having a thickness of from about 25 to about 500 nm.  
     
     
         4 . The capacitor of    claim 1    wherein said amorphous dielectric material is a perovskite-type oxide having the formula ABO 3  wherein B is at least one acidic oxide containing a metal selected from Group IVB, VB, VIB, VIIB or IB of the Periodic Table of Elements, and A is at least one additional cation having a positive formal charge of from about 1 to about 3.  
     
     
         5 . The capacitor of    claim 4    wherein said perovskite-type oxide is a titanate-based dielectric, a manganate-based material, a cuprate-based material, a tungsten bronze-type niobate, tantalate or titanate, or a layered bismuth-tantalate, -niobate or -titanate.  
     
     
         6 . The capacitor of    claim 1    wherein said amorphous dielectric material is barium strontium titanate, barium titanate, lead zirconium titanate, tantalum titanate, lead lanthanum titanate, strontium titanate, barium strontium niobate, barium zirconium titanate or barium titanium niobate.  
     
     
         7 . The capacitor of    claim 1    wherein said amorphous dielectric material is barium strontium titanate or barium zirconium titanate.  
     
     
         8 . The capacitor of    claim 1    wherein said electrodes are composed of a conductive material.  
     
     
         9 . The capacitor of    claim 8    wherein said conductive material is composed of the same or different material selected from the group consisting of TaN, Pt, Ir, ruthenium oxide, Al, Au , Cu, Ta, TaSiN and combinations or multilayers thereof.  
     
     
         10 . An integrated circuit chip having multiple wiring levels each of said wiring levels being separated by an insulating material, wherein a capacitor in accordance to    claim 1    is formed over an insulating material which separates the capacitor from the multiple wiring levels of the integrated circuit chip.  
     
     
         11 . The integrated circuit chip according to    claim 10    wherein the amorphous dielectric material of said capacitor is fabricated at temperatures below 450° C.  
     
     
         12 . The integrated circuit chip according to    claim 10    wherein the amorphous dielectric material of said capacitor is a thin film having a thickness of from about 25 to about 500 nm.  
     
     
         13 . The integrated circuit chip according to    claim 10    wherein said amorphous dielectric material of said capacitor is a perovskite-type oxide having the formula ABO 3  wherein B is at least one acidic oxide containing a metal selected from Group IVB, VB, VIB, VIIB or IB of the Periodic Table of Elements, and A is at least one additional cation having a positive formal charge of from about 1 to about 3.  
     
     
         14 . The integrated circuit chip according to    claim 10    wherein said perovskite-type oxide is a titanate-based dielectric, a manganate-based material, a cuprate-based material, a tungsten bronze niobate, titanate or tantalate, or a layered bismuth tantalate, -niobate or -titanate.  
     
     
         15 . The integrated circuit chip according to    claim 10    wherein said amorphous dielectric material of said capacitor is barium strontium titanate, barium titanate, lead zirconium titanate, tantalum titanate, lead lanthanum titanate, strontium titanate, barium strontium niobate, barium zirconium titanate or barium strontium tantalate.  
     
     
         16 . The integrated circuit chip according to    claim 10    wherein said amorphous dielectric material of said capacitor is barium strontium titanate or barium zirconium titanate.  
     
     
         17 . The integrated circuit chip according to    claim 10    wherein said insulating material is composed of a oxide, nitride or any other organic or inorganic insulating material.  
     
     
         18 . The integrated circuit chip according to    claim 10    wherein said wiring levels is composed of a conductive material.  
     
     
         19 . The integrated circuit of    claim 18    wherein said conductive material is the same or different and is selected from the group consisting of TaN, Pt, Ir, ruthenium oxide, Al, Au, Cu, Ta, TaSiN and mixtures or multilayers thereof.  
     
     
         20 . A method for forming a decoupling capacitor comprising the steps of: 
 (a) forming a film of an amorphous dielectric material having a dielectric constant of 10 or greater on a surface of an insulating layer;    (b) patterning the amorphous dielectric material into discrete sections; and    (c) depositing conducting electrodes between the patterned areas.    
     
     
         21 . The method of    claim 20    wherein step (a) includes deposition at temperatures under 450° C. and annealing at temperatures under 450° C.  
     
     
         22 . The method of    claim 20    wherein said deposition is carried out by chemical vapor deposition (CVD), physical vapor deposition, plasma-assisted CVD, low pressure CVD, high density plasma CVD, ionized PVP or chemical solution deposition (CSD).  
     
     
         23 . The method of    claim 22    wherein said deposition is by chemical solution deposition (CSD).  
     
     
         24 . The method of    claim 21    wherein said annealing is carried out in an oxidizing gas at a temperature of from about 150° to about 450° C. for a time period of from about 0.1 to about 4 hrs.  
     
     
         25 . The method of    claim 20    wherein step (b) is carried out by lithography.  
     
     
         26 . The method of    claim 20    wherein the amorphous dielectric material is a thin film having a thickness of from about 25 to about 500 nm.  
     
     
         27 . The method of    claim 20    wherein said amorphous dielectric material is a perovskite-type oxide having the formula ABO 3  wherein B is at least one acidic oxide containing a metal selected from Group IVB, VB, VIB, VIIB or IB of the Periodic Table of Elements, and A is at least one additional cation having a positive formal charge of from about 1 to about 3.  
     
     
         28 . The method of    claim 27    wherein said perovskite-type oxide is a titanate-based dielectric, a manganate-based material, a cuprate-based material, a tungsten bronze-type niobate, tantalate or titanate, or a layered bismuth-tantalate, -niobate or -titanate.  
     
     
         29 . The method of    claim 20    wherein said amorphous dielectric material is barium strontium titanate, barium titanate, lead zirconium titanate, tantalum titanate, lead lanthanum titanate, strontium titanate, barium titanate niobate, barium zirconium titanate or barium strontium niobate.  
     
     
         30 . The method of    claim 20    wherein said amorphous dielectric material is barium strontium titanate or barium zirconium titanate.  
     
     
         31 . A method for forming a decoupling capacitor comprising the steps of: 
 (a) depositing a layer of a conducting material on a surface of an insulating layer;    (b) patterning the conducting material into discrete sections; and    (c) forming an amorphous dielectric material having a dielectric constant of 10 or greater between the discrete sections.    
     
     
         32 . The method of    claim 31    wherein step (c) includes deposition at temperatures under 450 2  C. and annealing at temperatures under 450° C.  
     
     
         33 . The method of    claim 32    wherein said deposition is carried out by chemical vapor deposition (CVD), physical vapor deposition, plasma-assisted CVD, low pressure CVD, high density plasma CVD, ionized PVP or chemical solution deposition (CSD).  
     
     
         34 . The method of    claim 33    wherein said deposition is by CSD.  
     
     
         35 . The method of    claim 32    wherein said annealing is carried out in an oxidizing gas at a temperature of from about 200° to about 450° C. for a time period of from about 0.1 to about 4 hrs.  
     
     
         36 . The method of    claim 31    wherein step (b) is carried out by lithography.  
     
     
         37 . The method of    claim 31    wherein the amorphous dielectric material is a thin film having a thickness of from about 25 to about 500 nm.  
     
     
         38 . The method of    claim 31    wherein said amorphous dielectric material is a perovskite-type oxide having the formula ABO 3  wherein B is at least one acidic oxide containing a metal selected from Group IVB, VB, VIB, VIIB or IB of the Periodic Table of Elements, and A is at least one additional cation having a positive formal charge of from about 1 to about 3.  
     
     
         39 . The method of    claim 38    wherein said perovskite or tungsten bronze-type oxide is a titanate or tantalate-based dielectric, a manganate-based material, a cuprate-based material, a tungsten bronze-type niobate, tantalate or titanate, or a layered bismuth-tantalate, -niobate or -titanate.  
     
     
         40 . The method of    claim 31    wherein said amorphous dielectric material is barium strontium titanate, barium titanate, lead zirconium titanate, tantalum titanate, lead lanthanum titanate or strontium titanate, barium titanate niobate, barium zirconium titanate or barium strontium niobate.  
     
     
         41 . The method of    claim 31    wherein said amorphous dielectric material is barium strontium titanate or barium zirconium titanate.  
     
     
         42 . An integrated circuit (IC) semiconductor device comprising 
 a damascene structure, said damascene structure including alternating dielectric interlevels and wiring levels, wherein each of said wiring levels are interconnected by vias and contain a cap layer thereon; and    a patterned decoupling capacitor formed over the outermost wiring level, said patterned decoupling capacitor comprising a bottom electrode, an amorphous high dielectric constant thin film and an upper electrode.    
     
     
         43 . The IC semiconductor device of    claim 42    further comprising a metal fuse for separately connecting segments of said upper electrode to its voltage supply.  
     
     
         44 . The IC semiconductor device of    claim 42    further comprising sidewall spacers on each side of the patterned decoupling capacitor.  
     
     
         45 . A semiconductor device comprising 
 a damascene structure, said damascene structure including alternating dielectric interlevels and wiring levels, wherein each of said wiring levels are interconnected by vias and contain a cap layer thereon; and    a patterned decoupling capacitor formed over the wiring level underlying the outermost wiring level, said patterned stack decoupling capacitor comprising a bottom electrode, an amorphous high dielectric constant thin film and an upper electrode, said upper electrode being interconnected with said outermost wiring level by a via.    
     
     
         46 . The IC semiconductor device of    claim 45    further comprising a metal fuse for separately connecting segments of said upper electrode to its voltage supply.  
     
     
         47 . The IC semiconductor device of    claim 45    further comprising sidewall spacers on each side of the patterned decoupling capacitor.  
     
     
         48 . An integrated circuit (IC) semiconductor device comprising 
 a damascene structure, said damascene structure including alternating dielectric interlevels and wiring levels, wherein said outermost dielectric interlevel contains a trench therein;    a patterned decoupling capacitor formed in said trench, said patterned decoupling capacitor comprising a bottom electrode, an amorphous high dielectric constant thin film and an upper electrode; and    sidewall spacers on each side of the patterned decoupling capacitor.    
     
     
         49 . The IC semiconductor device of    claim 48    further comprising a metal fuse for separately connecting segments of said upper electrode to its voltage supply.