Method of forming a buried bitline in a vertical DRAM device

Abstract

A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.

Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is:  
     
         1 . A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device comprising the steps of: 
 (a) providing a structure having a dielectric layer on at least one surface of a p-type semiconducting material;    (b) forming pillar regions in said structure provided in (a) by etching trenches in said structure;    (c) forming a recessed liner in said trenches, wherein said recessed liner is composed of arsenic (As) or phosphorous (P) doped glass;    (d) forming a first oxide layer over the entire structure;    (e) annealing the structure so as to diffuse As and P into said semiconducting material and said pillar regions;    (f) oxidizing the structure provided in (e) so as to form a second oxide layer lining said pillars of said semiconducting material and to pile-up said As or P dopants in a region beneath said second oxide layer;    (g) removing said first oxide layer, said second oxide layer and any remaining recessed liner from said trenches; and    (h) etching said semiconducting material in said trenches so as to provide separate outdiffused buried bitline regions which are formed on the pillars' sidewalls.    
     
     
         2 . The method of    claim 1    wherein said p-type semiconducting material is composed of Si, Ge, Ga, As, InAs, InP or other III/V compounds which are doped with a p-type dopant.  
     
     
         3 . The method of    claim 1    wherein said semiconducting material is composed of p-type Si.  
     
     
         4 . The method of    claim 1    wherein said dielectric layer is composed of a dielectric material selected from the group consisting of SiO 2 , Si 3 N 4 , a polyimide, a paralene, a silicon-containing polymer, diamond, diamond-like carbon, fluorinated diamond-like carbon and composites thereof.  
     
     
         5 . The method of    claim 1    wherein said dielectric layer is composed of a composite of Si 3 N 4  and SiO 2 .  
     
     
         6 . The method of    claim 1    wherein said trench regions are formed by lithography and dry etching.  
     
     
         7 . The method of    claim 1    wherein said first oxide layer and said recessed liner are removed prior to conducting said oxidation step.  
     
     
         8 . The method of    claim 7    wherein said pillars provided in (b) have a starting thickness which is greater than the thickness of the pillars after said oxidation step.  
     
     
         9 . The method of    claim 1    wherein said annealing step is carried out by rapid thermal annealing (RTA) in an inert ambient at a temperature greater than 950° C.  
     
     
         10 . The method of    claim 9    wherein said RTA is carried out in argon.  
     
     
         11 . The method of    claim 9    wherein said RTA is carried out at a temperature of from about 1000° to about 1200° C. for a time period of less than about 2 minutes.  
     
     
         12 . The method of    claim 1    wherein said oxidation step is carried out by wet oxidation using an oxygen-containing ambient at a temperature of less than 950° C.  
     
     
         13 . The method of    claim 12    wherein said oxygen-containing ambient is steam.  
     
     
         14 . The method of    claim 12    wherein said wet oxidation is carried out at a temperature of from about 700° to about 945° C. for a time period of less than about 5 minutes.  
     
     
         15 . A vertical semiconductor memory device comprising: a p-type semiconducting material; an array of cells having pillars formed on said p-type semiconducting material, said pillars extending upward and being arranged in rows and columns, each of said pillars having an upper region doped with a n-type of impurity, a middle region which is composed of said p-type semiconducting material, and separate, lower regions outdiffused from the pillars' sidewalls which are doped with As and P, said middle region being continuous with the semiconducting material; 
 and gate regions positioned adjacent to said pillars.    
     
     
         16 . The vertical semiconductor memory device of    claim 15    wherein said semiconducting material and said middle region are composed of Si, Ge, Ga, As, InAs, InP or other III/V compounds which are doped with a p-type dopant.  
     
     
         17 . The vertical semiconductor memory device of    claim 16    wherein said semiconducting material and said middle region are composed of p-type Si.  
     
     
         18 . The vertical semiconductor memory device of    claim 15    wherein a gate oxide is formed between said pillars and said gate regions.  
     
     
         19 . The vertical semiconductor memory device of    claim 15    wherein said gate regions are composed of doped polysilicon.  
     
     
         20 . The vertical semiconductor memory device of    claim 15    wherein said lower regions have a low resistance at the highest possible concentration of As or P.