Method of manufacturing interconnect

Abstract

A method of manufacturing an interconnect. A wafer having an edge region and an interior region is provided. An insulating layer is formed on the wafer. An opening penetrating through the insulating layer in the interior region is formed and a portion of the insulating layer is removed to expose the surface of the wafer in the edge region, simultaneously. A conductive layer is formed on the insulating layer and the wafer exposed by the insulating layer and fills the opening. The conductive layer is patterned to form a wire in the opening.

What is claimed is:  
     
         1 . A method of manufacturing an interconnect on a wafer, wherein the wafer has an edge region and an interior region, the method comprising the steps of: 
 forming an insulating layer on the wafer having an interior region and a edge region;    forming an opening penetrating through the insulating layer in the interior region and removing a portion of the insulating layer to expose a surface of the wafer in the edge region, simultaneously;    forming a conductive layer on the insulating layer and the wafer exposed by the insulating layer and filling the opening; and    patterning the conductive layer to form a wire in the opening.    
     
     
         2 . The method of    claim 1   , wherein the opening includes a via hole.  
     
     
         3 . The method of    claim 1   , wherein the opening includes a node contact hole.  
     
     
         4 . The method of    claim 1   , wherein the step of forming the opening and removing the portion of the insulating layer comprises the steps of: 
 forming a positive photoresist on the insulating layer;    performing a first exposure step to from a first exposure region in the positive photoresist above the subsequently formed opening;    performing a second exposure step to form a second exposure region in the positive photoresist in the edge region;    removing the first and the second exposure regions until a portion of the insulating layer is exposed;    removing a portion of the insulating layer exposed by the positive resistor to form the opening and to expose the edge region of the wafer; and    removing the remaining positive photoresist.    
     
     
         5 . The method of    claim 4   , wherein the first and the second exposure steps are performed in the different steppers.  
     
     
         6 . The method of    claim 4   , wherein the second exposure step is performed without using any mask.  
     
     
         7 . The method of    claim 4   , wherein the second exposure step is performed by using a blank mask.  
     
     
         8 . The method of    claim 1   , wherein a material of the conductive layer can be polysilicon.