Integrated memory having a bit line reference voltage, and a method for producing the bit line reference voltage

Abstract

A semiconductor memory, in particular a ferroelectric semiconductor memory, has a differential write/read amplifier which is connected, via transfer transistors, to a bit line pair. The bit line pair includes a bit line and a corresponding reference bit line. The differential write/read amplifier is for reading data from and writing data to the memory capacitor (MC). In order to improve the accuracy of the bit line reference voltage, a main reference bit line is connected, via a charge switching element, to a reference voltage. At least one further reference bit line is connected to the main reference bit line via an equalization switching element for charge equalization between the reference bit lines.

We claim:  
     
         1 . An integrated memory, comprising: 
 word lines;    bit line pairs, each one of said bit line pairs including a first bit line and a reference bit line for receiving a bit line reference voltage, said reference bit line of one of said bit line pairs defining a main reference bit line;    intersections defined by locations where said word lines and said bit line pairs intersect;    memory capacitors disposed adjacent said intersections of said word lines and said bit line pairs, a particular one of said memory capacitors disposed adjacent a particular one of said word lines and adjacent a particular one of said bit line pairs, said particular one of said bit line pairs including a particular one of said first bit lines and a particular one of said reference bit lines;    a selection transistor having a control electrode connected to said particular one of said word lines, said selection transistor connecting said particular one of said memory capacitors to said particular one of said first bit lines;    transfer transistors connected to said particular one of said bit line pairs;    a differential write/read amplifier connected, by said transfer transistors, to said particular one of said bit line pairs for reading data from and writing data to said particular one of said memory capacitors;    a charge switching element for receiving a reference voltage and for connecting said main reference bit line to the reference voltage; and    an equalization switching element;    said reference bit line of one of said bit line pairs defining an additional reference bit line having a parasitic capacitance, said main reference bit line having a parasitic capacitance;    said equalization switching element for connecting said additional reference bit line to said main reference bit line to equalize charge between said parasitic capacitance of said main reference bit line and said parasitic capacitance of said additional reference bit line.    
     
     
         2 . The memory according to    claim 1   , comprising a reference voltage source providing the reference voltage to said charge switching element.  
     
     
         3 . The memory according to    claim 2   , comprising: 
 three equalization switching elements;    said reference bit lines of three of said bit line pairs defining three further reference bit lines;    said three equalization switching elements connecting said main reference bit line to said three further reference bit lines for charge equalization.    
     
     
         4 . The memory according to    claim 1   , comprising: 
 three equalization switching elements;    said reference bit lines of three of said bit line pairs defining three further reference bit lines;    said three equalization switching elements connecting said main reference bit line to said three further reference bit lines for charge equalization.    
     
     
         5 . The memory according to    claim 4   , wherein said three equalization switching elements are connected in series.  
     
     
         6 . The memory according to    claim 1   , wherein said charge switching element is a p-channel transistor.  
     
     
         7 . The memory according to    claim 1   , wherein said memory capacitors are ferroelectric capacitors.  
     
     
         8 . A method for producing a reference voltage on reference bit lines of an integrated memory, which comprises: 
 providing an integrated memory including memory capacitors, a differential amplifier for reading data from one of the memory capacitors, a bit line pair including a first bit line and a corresponding reference bit line for receiving a bit line reference voltage, a main reference bit line having a parasitic capacitance, and at least one further reference bit line having a parasitic capacitance;    connecting the differential amplifier to the bit line pair;    connecting a reference voltage to the main reference bit line;    disconnecting the reference voltage from the main reference bit line; and    connecting the at least one further reference bit line in parallel with the main reference bit line to: 
 connect the parasitic capacitance of the main reference bit line and the parasitic capacitance of the further reference bit line in parallel,  
 equalize charge stored in the parasitic capacitance of the main reference bit line and in the parasitic capacitance of the further reference bit line, and  
 split the reference voltage into a number of bit line reference voltages of equal magnitude.  
   
     
     
         9 . The method according to    claim 8   , which comprises, after the charge has been equalized, using at least one equalization switching element to disconnect the at least one further reference bit line from the main reference bit line.  
     
     
         10 . The method according to    claim 8   , which comprises providing the memory capacitors as ferroelectric capacitors.