Memory cell of the EEPROM type having its threshold adjusted by implantation

Abstract

A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

We claim:  
     
         1 . A storage device, comprising: 
 a circuitry transistor formed in a semiconductor substrate; and    a non-volatile EEPROM memory cell formed in the semiconductor substrate, the memory cell including a storage transistor and an associated selection transistor, the storage transistor having a first polysilicon layer underlying and isolated from a second polysilicon layer, the first polysilicon layer being coupled, by tunnel oxide, to a tunnel area placed in a channel region of said semiconductor substrate, the channel region having a first type of conductivity and being positioned between a drain region and a source region, the storage transistor also including an electrical continuity region with a second type of conductivity extending from said tunnel area to partly overlap said drain region; wherein said channel region includes an implanted region at a heavier dopant dosage than the semiconductor substrate.    
     
     
         2 . A device according to  claim 1 , wherein said implanted region includes a dopant of the P type.  
     
     
         3 . A device according to  claim 2 , wherein said dopant includes boron ions.  
     
     
         4 . A device according to  claim 1 , wherein the circuitry transistor includes said first and second polysilicon layers and a region in said semiconductor substrate that includes an implant for adjusting a threshold of the circuitry transistor; wherein said implanted region of the storage transistor has substantially the same dosage as said implant for adjusting the threshold of the circuitry transistor.  
     
     
         5 . A device according to  claim 1 , wherein said implanted region spans an entire area of the semiconductor substrate occupied by the memory cell.  
     
     
         6 . A storage device, comprising: 
 a selection transistor formed in an active area of a semiconductor substrate having a first conductivity type; and    a storage transistor formed in the active area of the substrate and including:    first and second active regions having a second conductivity type and being formed in the active area on opposite sides of a channel region of the substrate;    a gate insulating layer positioned on the channel region;    a floating gate positioned on the gate insulating layer;    a control gate capacitively coupled to the floating gate; and    an implanted, first shallow region extending in the channel region from the first active region to the second active region and having a depth in the substrate that is less than a depth in the substrate to which the first active region extends.    
     
     
         7 . The device of  claim 6  wherein the first shallow region and substrate have a P-type conductivity and the first and second active regions have an N-type conductivity.  
     
     
         8 . The device of  claim 6  wherein the gate insulating layer includes a tunnel region of reduced width and the first active region includes a capacitor implant region that extends under the tunnel region, the first shallow region extending from the capacitor implant region to the second active region.  
     
     
         9 . The device of  claim 8  wherein the first active region is a drain region and the second active region is a source region.  
     
     
         10 . The device of  claim 6  wherein the selection transistor includes a third active region formed in the active area of the substrate, a channel region defined between the first and third active regions, and a control gate formed above the channel region of the selection transistor.  
     
     
         11 . The device of  claim 10  wherein the selection transistor includes an implanted, second shallow region that extends between the first and third active regions.  
     
     
         12 . The device of  claim 6  wherein the storage transistor includes a dielectric layer formed on the floating gate and under the control gate, thereby capacitively coupling the floating and control gates.  
     
     
         13 . A storage device, comprising: 
 first and second active regions formed in an active area of a semiconductor substrate having a first conductivity type, the first and second active regions having a second conductivity type and being formed in the active area on opposite sides of a channel region of the substrate, and the first active region includes a capacitor implant region that extends under the tunnel region;    a gate insulating layer positioned on the channel region and having a tunnel region of reduced width;    a floating gate positioned on the gate insulating layer;    a control gate capacitively coupled to the floating gate; and    a first implanted region extending in the channel region from the capacitor implant region to the second active area and having a heavier dopant dosage than the substrate.    
     
     
         14 . The device of  claim 13  wherein the first implanted region and substrate have a P-type conductivity and the first and second active regions have an N-type conductivity.  
     
     
         15 . The device of  claim 13  wherein the first active region is a drain region and the second active region is a source region.  
     
     
         16 . The device of  claim 13 , further comprising a selection transistor that includes a third active region formed in the active area of the substrate, a channel region defined between the first and third active regions, and a control gate formed above the channel region of the selection transistor.  
     
     
         17 . The device of  claim 16  wherein the selection transistor includes a second implanted region that extends between the first and third active regions and has a heavier dopant dosage than the substrate.  
     
     
         18 . The device of  claim 13  wherein the storage transistor includes a dielectric layer formed on the floating gate and under the control gate, thereby capacitively coupling the floating and control gates.