Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates

Abstract

A method for producing a stress-engineered substrate includes selecting first and second materials for forming the substrate. An epitaxial material for forming a heteroepitaxial layer is then selected. If the lattice constant of the heteroepitaxial layer (a epi ) is greater than that (a sub ) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under “compressive stress” (negative stress) at all temperatures of concern. On the other hand, if the lattice constant of the heteroepitaxial layer (a epi ) is less than that (a sub ) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under “tensile stress” (positive stress). The temperatures of concern range from the annealing temperature to the lowest temperature where dislocations are still mobile.

What is claimed is:  
     
         1 . A method for producing a stress-engineered substrate, comprising the steps of: 
 a) selecting first and second materials for forming said substrate, said first material having a first lattice constant;    b) selecting an epitaxial material for forming a heteroepitaxial layer, said epitaxial material having a second lattice constant;    c) comparing said second lattice constant to said first lattice constant to determine which lattice constant is greater;    d) keeping, when said second lattice constant is greater than said first lattice constant, said heteroepitaxial layer under compressive stress for a range of temperatures, said range of temperatures being from an annealing temperature of said substrate to a lowest temperature where dislocations are still mobile in said heteroepitaxial layer and    e) keeping, when said second lattice constant is less than said first lattice constant, said heteroepitaxial layer under tensile stress for a range of temperatures, said range of temperatures being from an annealing temperature of said substrate to a lowest temperature where dislocations are still mobile in said heteroepitaxial layer.    
     
     
         2 . A method according to  claim 1 , further comprising: 
 f) growing said heteroepitaxial layer on said substrate.    
     
     
         3 . A method according to  claim 1 , further comprising: 
 f) bonding said first and second materials together via a first joining layer.    
     
     
         4 . A method according to  claim 3 , wherein said first material includes a template layer.  
     
     
         5 . A method according to  claim 4 , further comprising: 
 g) growing said heteroepitaxial layer on said template layer.    
     
     
         6 . A method according to  claim 1 , wherein said first material is GaAs and said second material is Si.  
     
     
         7 . A method according to  claim 1 , wherein said epitaxial material is InGaAs.  
     
     
         8 . A stress-engineered substrate, comprising: 
 a first stress control layer having a first lattice constant;    a second stress control layer;    a joining layer between said first stress control layer and said second stress control layer;    a heteroepitaxial layer having a second constant on said first control layer; and    means for choosing said first and second lattice constants, such that when said second lattice constant is greater than said first lattice constant, said heteroepitaxial layer is under compressive stress for a range of temperatures, said range of temperatures being from an annealing temperature of said substrate to a lowest temperature where dislocations are still mobile in said heteroepitaxial layer, and when said second lattice constant is less than said first lattice constant, said heteroepitaxial layer is under tensile stress for said range of temperatures.    
     
     
         9 . A stress-engineered substrate according to  claim 8 , wherein: 
 said first stress control layer is Si;    said second stress control layer is Ge; and    said heteroepitaxial layer is one of GaAs and InP.    
     
     
         10 . A stress-engineered substrate, comprising: 
 a first stress control layer;    a second stress control layer;    a joining layer between said first stress control layer and said second stress control layer;    a template layer on said first stress control layer, said template layer having a first lattice constant;    a heteroepitaxial layer having a second lattice constant on said template layer; and    means for choosing said first and second lattice constants, such that when said second lattice constant is greater than said first lattice constant, said heteroepitaxial layer is under compressive stress for a range of temperatures, said range of temperatures being from an annealing temperature of said substrate to a lowest temperature where dislocations are still mobile in said heteroepitaxial layer, and when said second lattice constant is less than said first lattice constant, said heteroepitaxial layer is under tensile stress for said range of temperatures.    
     
     
         11 . A stress-engineered substrate according to  claim 10 , wherein: 
 said first stress control layer is Si;    said second stress control layer is Ge;    said template layer is GaP; and    said heteroepitaxial layer is AlInGaP.