Vertical fuse structure for integrated circuits and a method of disconnecting the same

Abstract

A vertical fuse structure and methods for customization of integrated circuits include a substantially vertically-oriented interconnect structure or “fuse” which provides for a more densely packed and thus smaller programmable integrated circuit. In a preferred embodiment, a vertical interconnect structure is fabricated by forming a first interconnect layer, forming an insulating layer over the first interconnect layer in which substantially vertically-oriented vias are patterned in contact with the first interconnect layer, filling the vias with a conductive plug, and forming a second interconnect layer over the insulating layer in contact with the conductive plug. The vertical interconnect structure is preferably disconnected by forming a narrow, substantially vertical disconnect cavity through the second interconnect layer and a portion of the conductive plug, thereby removing the connection between the second interconnect layer and the plug.

We claim:  
     
         1 . A method for disconnecting a circuit comprising: 
 providing on a substrate a first conductive layer, an insulating layer disposed over the first conductive layer, a second conductive layer disposed over the insulating layer and the first conductive layer, and a conductive link connecting the first conductive layer to the second conductive layer, the conductive link having an outer surface peripheral area where the conductive link electrically connects to the second conductive layer; and    forming a disconnect cavity through a portion of the second conductive layer and a portion of the conductive link such that electrical connection between the second conductive layer and the conductive link is removed, the disconnect cavity having a larger outer surface peripheral area than the outer surface peripheral area of the conductive link.    
     
     
         2 . A method according to  claim 1 , wherein the outer surface peripheral area of the disconnect cavity is in part determined based upon possible alignment errors that exist when forming the disconnect cavity.  
     
     
         3 . A method according to  claim 1 , wherein the step of providing is preceded by disposing a photoresist layer on the upper surface of the second conductive layer and providing for a disconnect hole in the photoresist layer.  
     
     
         4 . A method according to  claim 3 , wherein the step of forming is accomplished by etching away the portion of the second conductive layer and the portion of the conductive link using the disconnect hole as a guide.  
     
     
         5 . A method according to  claim 4 , wherein the disconnect hole exposes only the second conductive layer.  
     
     
         6 . A method according to  claim 1 , wherein the step forming is accomplished by irradiation.  
     
     
         7 . A method according to  claim 1 , further comprising the step of sealing the disconnect cavity.  
     
     
         8 . A method according to  claim 1  wherein the step of providing provides the conductive link as a plug in a via.  
     
     
         9 . A method according to  claim 8  wherein the step of providing provides a plug that has substantially vertical sidewalls, and the step of forming provides the disconnect cavity having substantially vertical sidewalls.  
     
     
         10 . A method according to  claim 1 , wherein an etching characteristic of the insulating layer is matched to an etching characteristic of the conductive link.  
     
     
         11 . A method according to  claim 1  wherein the step of forming substantially completely removes the plug and maintains the integrity of the first conductive layer.  
     
     
         12 . An interconnect apparatus for a fusible link array in an integrated circuit comprising: 
 a first signal line;    a conductive interconnect;    a second signal line;    insulating material disposed between the first signal line and the conductive interconnect and the second signal line and the conductive interconnect;    a first plug disposed within a first portion of the insulating material that electrically connects the first signal line to the conductive interconnect; and    a second plug disposed within a second portion of the insulating material different from the first portion which originally electrically connected the conductive interconnect to the second signal line, and wherein subsequently a portion of the second plug has been removed, thereby preventing an electrical connection between the conductive interconnect and the second signal line.    
     
     
         13 . An apparatus according to  claim 12  wherein the first signal line and the second signal line are disposed on a same semiconductor layer.  
     
     
         14 . An apparatus according to  claim 12  wherein the first signal line and the second signal line are disposed on a different semiconductor layer.  
     
     
         15 . An apparatus according to  claim 12  further including: 
 a third signal line;  
 insulating material disposed between the third signal line and the conductive interconnect;  
 a third plug disposed within a third portion of the insulating material that electrically connects the third signal line to the conductive interconnect.  
 
     
     
         16 . An apparatus according to  claim 15 , wherein a portion of the third plug has been removed, thereby preventing an electrical connection between the conductive interconnect and the third signal line.  
     
     
         17 . An apparatus according to  claim 12  wherein the first and second plugs are disposed in vias formed in the insulator, wherein the electrical disconnection is caused by a disconnect cavity, and the first and second plugs and the disconnect cavity have substantially vertical sidewalls.  
     
     
         18 . An apparatus according to  claim 12  wherein an etching characteristic of the insulating material is matched to an etching characteristic of the second plug.  
     
     
         19 . An apparatus according to  claim 12  wherein substantially completely all of the second plug is removed to prevent the electrical connection between the conductive interconnect and the second signal line.  
     
     
         20 . An interconnect apparatus for a fusible link array in an integrated circuit comprising: 
 an input line;    an output line that crosses the input line at a predetermined position, the input line and the output line disposed on different semiconductor layers;    an insulating layer disposed between the input line and the output line;    a plug disposed at the predetermined position and within a first portion of the insulating material between the input line and the output line, the plug originally providing an electrically connection of the input line to the output line, and wherein subsequently a portion of the plug has been removed, thereby preventing the electrical connection between the input line and the output line.    
     
     
         21 . An apparatus according to  claim 12  wherein substantially completely all of the plug is removed to prevent the electrical connection between the input line and the output line.