Thermally stable polycrystal to single crystal electrical contact structure

Abstract

A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.

We claim:  
     
         1 . A method for forming a thermally stable ohmic contact structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor, the method comprising the step of: 
 forming at least one region of dielectric material between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.    
     
     
         2 . The method according to  claim 1 , further comprising the step of: 
 forming at least one region of dielectric material within the region of polycrystalline semiconductor parallel to the layer of dielectric material between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor.    
     
     
         3 . The method according to  claim 1 , wherein the at least one region of dielectric material has a thickness of about 0.2 nm to about 2.0 nm.  
     
     
         4 . The method according to  claim 1 , wherein the at least one region of dielectric material is deposited on the monocrystalline region.  
     
     
         5 . The method according to  claim 1 , wherein the dielectric material includes at least one nitride.  
     
     
         6 . The method according to  claim 5 , wherein the at least one region of dielectric material is formed through self-limiting nitridation of the monocrystalline region.  
     
     
         7 . The method according to  claim 5 , wherein the at least one region of dielectric material is formed by treating the monocrystalline region with ammonia.  
     
     
         8 . The method according to  claim 1 , wherein the dielectric material includes at least one oxide.  
     
     
         9 . The method according to  claim 8 , wherein the oxide is formed by treating the monocrystalline semiconductor with oxygen.  
     
     
         10 . The method according to  claim 9 , wherein treatment of the monocrystalline semiconductor is carried out at a temperature of less than 700° C.  
     
     
         11 . The method according to  claim 1 , wherein the structure includes a plurality of regions of polycrystalline semiconductor arranged in layers and the method further comprises the steps of: 
 forming at least one region of dielectric material adjacent at least a portion of at least one region of polycrystalline semiconductor.    
     
     
         12 . The method according to  claim 11 , wherein the at least one region of dielectric material is formed between at least two regions of polycrystalline semiconductor.  
     
     
         13 . The method according to  claim 11 , including at least two regions of dielectric material formed between at least two regions of polycrystalline semiconductor and between the region of monocrystalline semiconductor and a region of polycrystalline semiconductor.  
     
     
         14 . The method according to  claim 11 , wherein the at least one layer of dielectric material is formed between two portions of the at least one region of polycrystalline semiconductor.  
     
     
         15 . The method according to  claim 1 , wherein the at least one layer of polycrystalline semiconductor material has a grain size of less than about 10 nm or greater than about 10 nm.  
     
     
         16 . The method according to  claim 1 , wherein the at least one region of dielectric material has a thickness of about 0.2 nm to about 2.0 nm.  
     
     
         17 . The method according to  claim 1 , wherein the electrically insulating material is deposited on a sidewall of a trench.  
     
     
         18 . A method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor, the method comprising the step of: 
 providing at least one region of electrically conducting material between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor.    
     
     
         19 . The method according to  claim 18 , wherein the at least one region of electrically conducting material includes at least one layer of electrically conducting material, the method further comprising the step of: 
 depositing the at least one layer of electrically conducting material within the region of polycrystalline semiconductor parallel to the at least one layer of electrically conducting material between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor.    
     
     
         20 . The method according to  claim 18 , wherein the at least one region of electrically conducting material is amorphous.  
     
     
         21 . The method according to  claim 18 , wherein the at least one region of electrically conducting material is crystalline, has a different lattice constant from the monocrystalline semiconductor material, and will not grow epitaxially.  
     
     
         22 . The method according to  claim 18 , wherein the at least one region of electrically conducting material includes at least one member selected from the group consisting of group IV metals, oxides of group IV metals, suicides of group IV metals, Ti, and TiN.  
     
     
         23 . The method according to  claim 18 , wherein the structure includes a plurality of regions of polycrystalline semiconductor arranged in layers and the method further comprises the steps of: 
 forming at least one region of electrically conducing material adjacent at least a portion of at least one of the regions of polycrystalline semiconductor.    
     
     
         24 . The method according to  claim 23 , wherein the at least one region of electrically conducting material is formed between at least two regions of polycrystalline semiconductor.  
     
     
         25 . The method according to  claim 23 , including at least two regions of electrically conducting material formed between at least two regions of polycrystalline semiconductor and between the region of monocrystalline semiconductor and a region of polycrystalline semiconductor.  
     
     
         26 . The method according to  claim 23 , wherein the at least one layer of electrically conducting material is formed between two portions of the at least one region of polycrystalline semiconductor.  
     
     
         27 . The method according to  claim 18 , wherein the at least one layer of polycrystalline semiconductor material has a grain size of less than about 10 nm or greater than about 10 nm.  
     
     
         28 . The method according to  claim 18 , wherein the electrically insulating material is deposited on a sidewall of a trench.  
     
     
         29 . A method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor, the method comprising the step of: 
 depositing at least one region of a polycrystalline semiconductor with a lattice mismatch with respect to the monocrystalline semiconductor between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor.    
     
     
         30 . The method according to  claim 29 , wherein the at least one region of polycrystalline semiconductor with the lattice mismatch is SiGe and the monocrystalline semiconductor is Si.  
     
     
         31 . The method according to  claim 29 , wherein the electrically insulating material is deposited on a sidewall of a trench.  
     
     
         32 . A method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor, the method comprising the steps of: 
 depositing the region of polycrystalline semiconductor material on a surface of the region of monocrystalline semiconductor; and    introducing at least one impurity into the polycrystalline semiconductor material being deposited in the polycrystalline region during deposition of the polycrystalline semiconductor.    
     
     
         33 . The method according to  claim 32 , wherein the at least one impurity includes at least one member selected from the group consisting of oxygen and nitrogen.  
     
     
         34 . The method according to  claim 32 , further comprising the step of: 
 exposing the monocrystalline semiconductor, polycrystalline semiconductor and at least one impurity to a temperature above about 500° C.    
     
     
         35 . The method according to  claim 32 , wherein the electrically insulating material is deposited on a sidewall of a trench.  
     
     
         36 . A method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor, the method comprising the step of: 
 depositing at least one region of amorphous semiconductor material adjacent the region of monocrystalline semiconductor material; and    crystallizing the amorphous semiconductor material.    
     
     
         37 . The method according to  claim 36 , wherein crystallization of the amorphous semiconductor material is carried out at a temperature of about 500° C. to about 600° C. at a pressure of from about 150 torr to about 600 torr.  
     
     
         38 . The method according to  claim 38 , further comprising the step of: 
 providing at least one region of an electrically insulating material on the monocrystalline semiconductor region prior to depositing the amorphous semiconductor material.    
     
     
         39 . The method according to  claim 38 , wherein the at least one region of an electrically insulating material is an oxide provided by treating the region of monocrystalline semiconductor with oxygen.  
     
     
         40 . The method according to  claim 39 , wherein crystallization of the amorphous semiconductor is carried out a temperature such that the at least one region of oxide prevents epitaxial growth of the amorphous semiconductor.  
     
     
         41 . The method according to  claim 39 , wherein crystallization of the amorphous semiconductor is carried out a temperature sufficient to cause a break-up of the at least one region of oxide.  
     
     
         42 . The method according to  claim 39 , wherein the oxide is formed with a rapid thermal oxidation.  
     
     
         43 . The method according to  claim 42 , wherein the rapid thermal oxidation comprises the step of: 
 ramping monocrystalline semiconductor material from a temperature of about 25° C. to a temperature about 500° C. to about 700° C. at a rate of about 5° C./sec to 150° C./sec, holding at 500° C. to 700° C. for a time of about 1 sec to about 1 min in an atmosphere including O 2  at a concentration of about 5% to 100%.    
     
     
         44 . The method according to  claim 38 , wherein the amorphous semiconductor material is deposited on the monocrystalline semiconductor region at a temperature of less than about 575° C.  
     
     
         45 . The method according to  claim 38 , wherein the at least one region of an electrically insulating material includes at least one material selected from the group consisting of an oxide, a nitride, and a nitridized oxide.  
     
     
         46 . The method according to  claim 38 , wherein the at least one region of an electrically insulating material includes SiGe.  
     
     
         47 . The method according to  claim 38 , wherein the region of electrically insulating material has a thickness of less than about 20 Å.  
     
     
         48 . The method according to  claim 38 , wherein the region of electrically insulating material has a thickness of less than about 10 Å.  
     
     
         49 . The method according to  claim 45 , wherein the electrically insulating material is a nitride and is formed according to a process that includes the steps of: 
 annealing at least a portion of a surface of the monocrystalline semiconductor in an ammonia containing atmosphere at a temperature of about 300° C. to about 800° C.    
     
     
         50 . The method according to  claim 45 , wherein the electrically insulating material is a nitridized oxide and is formed according to a process that includes the steps of: 
 annealing at least a portion of a surface of the monocrystalline semiconductor in an N 2 O containing atmosphere at a temperature of about 20° C.    
     
     
         51 . The method according to  claim 36 , further comprising the step of: 
 providing at least one region of an electrically conducting material on the monocrystalline semiconductor region prior to depositing the amorphous semiconductor material.    
     
     
         52 . The method according to  claim 51 , wherein the electrically conducting material is crystalline and has a different crystal lattice structure as compared to the monocrystalline semiconductor, such that the electrically conducting material will not form an epitaxial layer.  
     
     
         53 . The method according to  claim 51 , wherein the electrically conducting material includes at least one material selected from the group consisting of SiGe, Ge, SiGe alloy, SIC, other group IV elements and alloys containing other group IV elements.  
     
     
         54 . The method according to  claim 51 , wherein the electrically conducting material includes SiGe, wherein the percentage of Ge in the SiGe is about 30% to about 10%.  
     
     
         55 . The method according to  claim 36 , further comprising the step of: 
 providing at least one region of an amorphous material on the monocrystalline semiconductor region prior to depositing the amorphous semiconductor material.    
     
     
         56 . The method according to  claim 55 , wherein the amorphous material deposited on the monocrystalline semiconductor includes at least one material selected from the group consisting of a metal oxide and a metal nitride.  
     
     
         57 . The method according to  claim 55 , wherein the amorphous material deposited on the monocrystalline semiconductor includes SnO or TiN.  
     
     
         58 . The method according to  claim 36 , wherein the electrically insulating material is deposited on a sidewall of a trench.  
     
     
         59 . A method for forming a thermally stable structure including a region of monocrystalline semiconductor and a region of polycrystalline semiconductor, the method comprising the step of: 
 suppressing grain growth of the polycrystalline semiconductor as it is deposited on the monocrystalline semiconductor.    
     
     
         60 . A semiconductor device, comprising: 
 a region of monocrystalline semiconductor;    a region of non-monocrystalline semiconductor; and    an interface layer between the monocrystalline semiconductor region and non-monocrystalline semiconductor region controlling grain growth of the polycrystalline semiconductor.    
     
     
         61 . The semiconductor device according to claim  63 , wherein the interface layer includes at least one oxide and is arranged on a trench sidewall of a DRAM device.