Barrier enhancement process for copper interconnects

Abstract

A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10μ to 100μ and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

We claim:  
     
         1 . A process for applying a metal to a microelectronic workpiece, the microelectronic workpiece including a surface in which are disposed one or more micro-recessed structures, the process comprising: 
 (d) forming a barrier layer on the surface of the microelectronic workpiece, including on the walls of the micro-recessed structures;    (e) forming an enhancement layer over the barrier layer, wherein said enhancement layer is comprised of a metal alloy; and    (f) electroplating a metal onto the enhancement layer so as to fill the micro-recessed structure.    
     
     
         2 . The process of  claim 1 , wherein the enhancement layer is formed using an electrochemical deposition process.  
     
     
         3 . The process of  claim 2 , wherein the electrochemical deposition process is selected from the group consisting of electroless and electroplating processes.  
     
     
         4 . The process of  claim 1 , wherein the enhancement layer is formed using a CVD process.  
     
     
         5 . The process of  claim 1 , wherein the enhancement layer is formed using a PVD process.  
     
     
         6 . The process of  claim 1 , wherein the enhancement layer is formed with a thickness of 100μ or less.  
     
     
         7 . The process of  claim 1 , wherein the enhancement layer is formed with a thickness in the range of from 10μ to 100μ thick.  
     
     
         8 . The process of  claim 1 , wherein the barrier layer so formed has seams, discontinuities or grain boundary defects, and wherein the enhancement layer conformally covers the barrier layer.  
     
     
         9 . The process of  claim 1 , wherein the enhancement layer is formed from a copper alloy.  
     
     
         10 . The process of  claim 9 , wherein the copper alloy is selected from the group consisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, and mixtures of such alloys.  
     
     
         11 . The process of  claim 1 , wherein the enhancement layer is formed from a binary alloy composition.  
     
     
         12 . The process of  claim 11 , wherein the alloy is Co—P.  
     
     
         13 . The process of  claim 1 , wherein the enhancement layer is formed from a tertiary alloy composition.  
     
     
         14 . The process of  claim 13 , wherein the alloy is Co—W—P.  
     
     
         15 . The process of  claim 1 , wherein the metal electroplated onto the enhancement layer is copper.  
     
     
         16 . The process of  claim 1 , further comprising: 
 (d) removing a portion of the metal from the surface of the microelectronic workpiece.    
     
     
         17 . The process of  claim 16 , wherein the removing is by chemical mechanical polishing.  
     
     
         18 . The process of  claim 1 , wherein the microelectronic workpiece is a silicon or gallium arsenide semiconductor wafer.  
     
     
         19 . A metallization layer formed in a microelectronic workpiece according to the process of  claim 1 .  
     
     
         20 . A process for applying a metal to a microelectronic workpiece, the microelectronic workpiece including a surface in which are disposed one or more micro-recessed structures, the process comprising: 
 (a) forming a barrier layer on the surface of the microelectronic workpiece, including on the walls of the micro-recessed structures;    (b) forming an enhancement layer of a metal alloy over the barrier layer;    (c) forming a seed layer over the enhancement layer; and    (d) electroplating a metal onto the enhancement layer so as to fill the micro-recessed structure.    
     
     
         21 . The process of  claim 20 , wherein the enhancement layer is formed using an electrochemical deposition process.  
     
     
         22 . The process of  claim 21 , wherein the electrochemical deposition process is selected from the group consisting of electroless and electroplating processes.  
     
     
         23 . The process of  claim 20 , wherein the enhancement layer is formed using a CVD process.  
     
     
         24 . The process of  claim 20 , wherein the enhancement layer is formed using a PVD process.  
     
     
         25 . The process of  claim 20 , wherein the enhancement layer is formed with a thickness of 100μ or less.  
     
     
         26 . The process of  claim 20 , wherein the enhancement layer is formed with a thickness in the range of from 10μ to 100μ thick.  
     
     
         27 . The process of  claim 20 , wherein the barrier layer so formed has seams, discontinuities or grain boundary defects, and wherein the enhancement layer conformally covers the barrier layer.  
     
     
         28 . The process of  claim 20 , wherein the enhancement layer is formed from a copper alloy.  
     
     
         29 . The process of  claim 28 , wherein the copper alloy is selected from the group consisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, and mixtures of such alloys.  
     
     
         30 . The process of  claim 20 , wherein the enhancement layer is formed from a binary alloy composition.  
     
     
         31 . The process of  claim 30 , wherein the alloy is Co—P.  
     
     
         32 . The process of  claim 20 , wherein the enhancement layer is formed from a tertiary alloy composition.  
     
     
         33 . The process of  claim 32 , wherein the alloy is Co—W—P.  
     
     
         34 . The process of  claim 20 , wherein the metal electroplated onto the enhancement layer is copper.  
     
     
         35 . The process of  claim 20 , further comprising: 
 (e) removing a portion of the metal from the surface of the microelectronic workpiece.    
     
     
         36 . The process of  claim 35 , wherein the removing is by chemical mechanical polishing.  
     
     
         37 . The process of  claim 20 , wherein the microelectronic workpiece is a silicon or gallium arsenide semiconductor wafer.  
     
     
         38 . A metallization layer formed in a microelectronic workpiece according to the process of  claim 20 .  
     
     
         39 . In a manufacturing line including a plurality of apparatus for the manufacture of microelectronic circuits or components, one or more apparatus of the plurality of apparatus being used for applying interconnect metallization in a damascene process to a surface of a microelectronic workpiece used to form the microelectronic circuits or components, the one or more apparatus comprising: 
 means for applying a barrier layer to a surface of the microelectronic workpiece using a first deposition process, wherein the barrier layer is generally unsuitable for bulk electrochemical deposition of the interconnect metallization;    means for applying an enhancement layer over the barrier layer using a second deposition process, wherein the enhancement layer formed from an alloy composition that is generally suitable for subsequent electrochemical application of a metal to a predetermined thickness representing a bulk portion of the interconnect metallization; and    means for electrochemical application of a metal over the enhancement layer.    
     
     
         40 . The manufacturing line of  claim 39 , wherein the means for applying the enhancement layer is equipment for electrochemical deposition.  
     
     
         41 . The manufacturing line of  claim 40 , wherein the means for applying the enchancement layer performs an electrochemical deposition process selected from the group consisting of electroless and electroplating processes.  
     
     
         42 . The manufacturing line of  claim 39 , wherein the means for applying the enhancement layer is equipment for CVD processing.  
     
     
         43 . The manufacturing line of  claim 39 , wherein the means for applying the enhancement layer is equipment for PVD processing.  
     
     
         44 . The manufacturing line of  claim 39 , wherein the means for applying the enhancement layer is capable of applying the enhancement layer conformally over the barrier layer to a thickness of 100μ or less.  
     
     
         45 . The manufacturing line of  claim 39 , wherein the enhancement layer is formed from a metal alloy selected from the group consisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P, and Co—W—P, and mixtures thereof.  
     
     
         46 . The manufacturing line of  claim 39 , the means for electrochemical application of a metal over the enhancement layer is capable of applying copper as the metal.  
     
     
         47 . The manufacturing line of  claim 39 , further comprising: 
 means for removing a portion of the metal from the surface of the microelectronic workpiece.    
     
     
         48 . The manufacturing line of  claim 47 , wherein the means for removing a portion of the metal comprises chemical mechanical polishing equipment.  
     
     
         49 . The manufacturing line of  claim 39 , wherein the microelectronic workpiece is a silicon or gallium arsenide semiconductor wafer.  
     
     
         50 . An apparatus for applying interconnect metallization in a damascene process to a surface of a microelectronic workpiece used to form microelectronic circuits or components, comprising: 
 means for applying a barrier layer to a surface of the microelectronic workpiece using a first deposition process, wherein the barrier layer is generally unsuitable for bulk electrochemical deposition of the interconnect metallization;    means for applying an enhancement layer over the barrier layer using a second deposition process, wherein the enhancement layer formed from an alloy composition that is generally suitable for subsequent electrochemical application of a metal to a predetermined thickness representing a bulk portion of the interconnect metallization; and    means for electrochemical application of a metal over the enhancement layer.    
     
     
         51 . The apparatus of  claim 50 , wherein the means for applying the enhancement layer is equipment for electrochemical deposition.  
     
     
         52 . The apparatus of  claim 51 , wherein the means for applying the enchancement layer performs an electrochemical deposition process selected from the group consisting of electroless and electroplating processes.  
     
     
         53 . The apparatus of  claim 51 , wherein the electrochemical deposition equipment comprises a chamber, one or more electrodes, one or more cathodes and a processing fluid to couple the one or more electrodes and the one or more cathodes to the microelectronic workpiece.  
     
     
         54 . The apparatus of  claim 53 , wherein the processing fluid is an electrolyte for electroplating copper or a metal alloy selected from the group consisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P, and Co—W—P, and mixtures.  
     
     
         55 . The apparatus of  claim 50 , wherein the means for applying the enhancement layer is capable of applying the enhancement layer conformally over the barrier layer to a thickness of 100μ or less.  
     
     
         56 . The apparatus of  claim 50 , wherein the enhancement layer is formed from a metal alloy selected from the group consisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P, and Co—W—P.  
     
     
         57 . The apparatus of  claim 50 , the means for electrochemical application of a metal over the enhancement layer is capable of applying copper as the metal.  
     
     
         58 . The apparatus of  claim 50 , wherein the means for applying the barrier layer is within a first chamber and the means for applying the enhancement layer is within a second chamber of the apparatus.  
     
     
         59 . The apparatus of  claim 50 , wherein the means for applying the enhancement layer is within a first chamber and the means for applying the metal over the enhancement layer is within a second chamber of the apparatus.  
     
     
         60 . The apparatus of  claim 50 , wherein the means for applying the enhancement layer is within a first chamber and the means for applying a metal over the enhancement layer comprises the same means within the first chamber of the apparatus.  
     
     
         61 . The apparatus of  claim 50 , wherein the microelectronic workpiece is a silicon or gallium arsenide semiconductor wafer.