Semiconductor integrated circuit device and a method of manufacturing the same

Abstract

A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device having MISFETs, formed on a substrate of an active region defined by an element isolation trench, wherein 
 an inclined surface which falls toward the side wall of the element isolation trench is formed on the surface of the substrate at the periphery of the active region, and the inclined surface includes a first inclined surface located at the center of the active region and a second inclined surface which is interposed between the first inclined surface and the side wall of the element isolation trench and is more gently inclined than the first inclined surface.    
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein the surface of an insulating film buried in the element isolation trench is recessed downward in the vicinity of the active region.  
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , wherein the end of a gate insulating film formed on the substrate of the active region extends to the lower end of the second inclined surface.  
     
     
         4 . The semiconductor integrated circuit device according to  claim 1 , wherein the end of a channel formed in the vicinity of the surface of the substrate of the active region extends to the lower end of the second inclined surface.  
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , wherein the concentration of an impurity introduced into the substrate of a region where the channel is formed is almost equal to those of the center portion of the active region and the first and second inclined surfaces.  
     
     
         6 . The semiconductor integrated circuit device according to  claim 1 , wherein the surface of the semiconductor substrate at the boundary between the center portion of the active region and the first inclined surface and the surface of the semiconductor substrate at the boundary between the second inclined surface and the side wall of the element isolation trench are rounded convex and the surface of the semiconductor substrate at the boundary between the first inclined surface and the second inclined surface is rounded concave.  
     
     
         7 . A semiconductor integrated circuit device having MISFETs, formed in an active region defined by an element isolation trench in the main surface of a substrate, wherein 
 the surface of the substrate in the shoulder portion of the element isolation trench includes first and second rounded convex surfaces and a rounded concave surface located between the first and second rounded convex surfaces, and the surface of an insulation film buried in the element isolation trench is recessed downward in the vicinity of the active region.    
     
     
         8 . The semiconductor integrated circuit device according to  claim 7 , wherein the thickness of a gate insulating film formed on the substrate in the shoulder portion of the element isolation trench is almost equal to the thickness of a gate insulating film formed on the substrate in the center portion of the active region.  
     
     
         9 . The semiconductor integrated circuit device according to  claim 7 , wherein the MISFET formed in the active region is of a surface channel type.  
     
     
         10 . The semiconductor integrated circuit device according to  claim 7 , wherein the MISFET formed in the active region is a MISFET for the selection of a memory cell forming part of the memory cells of a DRAM, and a capacitor element forming the other part of the memory cells of the DRAM is connected in series to the MISFET for the selection of a memory cell.  
     
     
         11 . The semiconductor integrated circuit device according to  claim 7 , wherein the size in a gate width direction of the active region is 0.2 μm or less.  
     
     
         12 . A method of manufacturing a semiconductor integrated circuit device comprising the steps of: 
 (a) forming a first silicon oxide film on the surface of a substrate made from monocrystal silicon by thermally oxidizing the substrate and then an oxidation resistant film on the first silicon oxide film, and selectively exposing the surface of the substrate by etching the oxidation resistant film and the first silicon oxide film of an element isolation region;    (b) forming a second silicon oxide film having a thickness larger than that of the first silicon oxide film on the surface of the substrate which is exposed in the above step (a) by thermally oxidizing the substrate;    (c) exposing the surface of the substrate in the element isolation region by etching the second silicon oxide film;    (d) forming a trench in the substrate of the element isolation region by etching the substrate exposed in the above step (c) and forming a third silicon oxide film on the inner wall of the trench by thermally oxidizing the substrate;    (e) forming a fourth silicon oxide film on the oxidation resistant film containing the inside of the trench and then an element isolation trench having the fourth silicon oxide film buried therein in the substrate of the element isolation region by polishing the fourth silicon oxide film using the oxidation resistant film as a stopper;    (f) removing the oxidation resistant film and introducing an impurity into the substrate to control the threshold voltage of a MISFET; and    (g) exposing the surface of the substrate by etching, and forming a gate insulating film on the surface of the substrate and further a gate electrode for the MISFET on the gate insulating film.    
     
     
         13 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , wherein the substrate is over-etched when the surface of the substrate is to be exposed in the step (a).  
     
     
         14 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , further comprising the step of recessing the end of the first silicon oxide film inward more than the end of the silicon nitride film by etching the surface of the substrate isotropically after the step (a) and prior to the step (b).  
     
     
         15 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , further comprising the step of densifying the fourth silicon oxide film buried in the trench by heating the substrate before or during the step (e).  
     
     
         16 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , wherein the step (e) includes the step of forming the fourth silicon oxide film on the oxidation resistant film containing the inside of the trench and removing the fourth silicon oxide film overlying the oxidation resistant film by etching using a photoresist film as a mask and the step of removing the photoresist film and polishing the fourth silicon oxide film overlying the trench using the oxidation resistant film as a stopper.  
     
     
         17 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , wherein the surface of the fourth silicon oxide film at the periphery of the element isolation trench is recessed downward by etching the surface of the fourth silicon oxide film buried in the element isolation trench isotropically when the substrate is to be etched in the step (g).  
     
     
         18 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , further comprising the step of introducing an impurity into the substrate to form wells after or during the step (g).  
     
     
         19 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , wherein the shoulder portion of the trench is etched at the same time when the trench is formed in the substrate of the element isolation region in the step (d).  
     
     
         20 . The method of manufacturing a semiconductor integrated circuit device according to  claim 12 , wherein the shoulder portion of the trench is rounded when the substrate is to be thermally oxidized in the step (d).  
     
     
         21 . A semiconductor integrated circuit device having MISFETs which comprise a gate electrode having a predetermined width in a first direction and formed across an active region through a gate insulating film in a second direction crossing the first direction on a semiconductor substrate of the active region surrounded by an element isolation trench, and a source and drain formed on the semiconductor substrate on both sides of the gate electrode, 
 the semiconductor integrated circuit device comprising: 
 (a) the active region having a first surface, a second surface and a third surface interposed between the first and second surfaces on the surface of the semiconductor substrate, the second surface constituting the side wall of the element isolation trench;  
 (b) a first insulating film formed in the element isolation trench;  
 (c) the gate insulting film formed on the first and third surfaces; and  
 (d) the gate electrode formed on the gate insulating film;  
   wherein an angle between the tangent line of the third surface and the first surface gradually increases and then gradually decreases from the first surface to the second surface in the second direction.    
     
     
         22 . The semiconductor integrated circuit device according to  claim 21 , wherein the angle between the tangent line of the third surface and the first surface gradually increases, gradually decreases and then increases again before the second surface.  
     
     
         23 . A semiconductor integrated circuit device having MISFETs each of which comprises a gate electrode having a predetermined width in a first direction and formed across an active region through a gate insulating film in a second direction crossing the first direction on a semiconductor substrate of the active region surrounded by an element isolation trench, and a source and drain formed on the semiconductor substrate on both sides of the gate electrode, 
 the semiconductor integrated circuit device comprising: 
 (a) the active region having a first surface, a second surface and a third surface interposed between the first and second surfaces on the surface of the semiconductor substrate, the second surface constituting the side wall of the element isolation trench;  
 (b) a first insulating film formed in the element isolation trench;  
 (c) the gate insulting film formed on the first and third surfaces;  
 (d) the gate electrode formed on the gate insulating film and extending over the first insulating film in the element isolation trench across the active region; and  
 (e) a semiconductor region formed on the surface of the active region and having a predetermined width in the depth direction of the semiconductor substrate on the first and third surfaces;  
   wherein the lower end of the semiconductor region on the second surface is situated below the lower end of the gate electrode on the second surface.