Plating method, plating solution, semiconductor device and process for producing the same

Abstract

A plating method comprising using a plating solution containing an additive satisfying the following conditions: 0.005× h 2 /W<D/κ<0.5×h 2 /w, and 0.01≦Θ≦0.7 wherein D is a diffusion coefficient of the additive; κ is a surface reaction rate of adsorption or consumption of the additive; h is a height of a trench or hole; w is the width of the trench or the radius of the hole; and Θ is a ratio of (plating film growth rate in the presence of additive)/(plating film growth rate in the absence of additive), is suitable for forming the plating metal in the trench or hole having the width of 1 μm or less (trench) or the radius of 1 μm or less (hole) without generating voids, and particularly suitable for producing semiconductor devices, which can have a multilayer structure of copper wiring layers formed on a semiconductor substrate by using the plating conditions, wherein at least one layer of copper wiring layers is plated in different conditions from the rest of the copper wiring layers.

What is claimed is:  
     
         1 . A semiconductor device obtained by a process comprising a step of forming a plating metal in a trench having a minimum width (w) of 10 −6  m or less, or a hole having a minimum radius (w) of 10 −6  m or less, the improvement wherein there is used a plating solution containing an additive which satisfies the following conditions:  
       0.005× h   2   /w<D/κ< 0.5× h   2   /w    
       wherein D is a diffusion coefficient (m 2 /sec) of the additive; κ is a surface reaction rate (m/sec) of adsorption or consumption of the additive; h is a height (m) of the trench or hole; and w is the minimum width (m) of the trench or the minimum radius (m) of the hole, and  
       0.01≦Θ≦0.7  
       wherein Θ is a ratio of (plating film growth rate in the presence of additive)/(plating film growth-rate in the absence of additive), or (plating current in the presence of additive)/(plating current in the absence of additive), at the same plating potential.  
     
     
         2 . A semiconductor device comprising a plurality of copper wiring layers formed on a semiconductor substrate, wherein at least one copper wiring layer has an element or amount ratio thereof or both in copper wiring different from the rest of copper wiring layers.  
     
     
         3 . A semiconductor device according to  claim 2 , wherein the copper wiring is formed by copper plating.  
     
     
         4 . A semiconductor device according to  claim 2 , wherein the amount ratio of element is obtained by changing the plating conditions, said plating conditions dependent on at least one of a composition of a plating solution, a concentration of at least one of additive and copper in the plating solution, a current density, and a flow rate of plating solution.  
     
     
         5 . A semiconductor device according to  claim 2 , wherein the amount ratio of element is obtained by observing elements using a secondary ion mass spectroscopy.