Partitionable embedded circuit test system for integrated circuit

Abstract

A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.

We claim:  
     
         1 . An apparatus for testing a memory embedded in an integrated circuit (IC), wherein said memory ( 12 ) includes a plurality of addressable memory cells and wherein said IC includes a logic circuit ( 14 , 16 ) linked to said memory for read and write accessing said memory, the apparatus comprising: 
 a test circuit ( 40 ) included in said IC for receiving input MIN, MAX data and for successively testing all memory cells of said memory having addresses within a range of addresses indicated by said input MIN, MAX data to determine whether each memory cell is defective, and    control means ( 21 ,  66  or  68  and  55 ) for supplying said MIN, MAX data to said test circuit.    
     
     
         2 . The apparatus in accordance with  claim 1  wherein said control means also supplies a START signal to said test circuit to tell it when to begin testing the memory cells of said memory.  
     
     
         3 . The apparatus in accordance with  claim 1  further comprising switch means ( 42 - 44 ) included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memory and by connecting said test circuit to said memory so that said test circuit can test the memory cells of said memory, 
 wherein said control means supplies said MODE control signal to said switch means.  
 
     
     
         4 . The apparatus in accordance with  claim 1  wherein said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective.  
     
     
         5 . The apparatus in accordance with  claim 1  wherein said test circuit continuously asserts an output FAIL signal after determining that any one of said memory cells is defective.  
     
     
         6 . The apparatus in accordance with  claim 1   wherein said control means supplies a DIAG signal to said test circuit, and    wherein in response to a state of said DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells.    
     
     
         7 . The apparatus in accordance with  claim 6  wherein said control means also monitors said DONE signal to determine when said test circuit has completed a test.  
     
     
         8 . The apparatus in accordance with  claim 6   wherein said test circuit continuously asserts an output FAIL signal after determining that any one of said memory cells is defective,    wherein said test circuit pulses an output CERR signal whenever it determines any one of said memory cells is defective, and selectively asserts a DONE signal when it has completed testing all memory addresses.    
     
     
         9 . The apparatus in accordance with  claim 8   wherein said control means monitors said DONE signal to determine when said test circuit has completed a test,    wherein said control means monitors said FAIL signal to determine whether any one of said memory cells is defective, and    wherein said control means monitors said DONE signal to determine which of said memory cells is defective.    
     
     
         10 . The apparatus in accordance with  claim 1   wherein said addressable memory cells are arrayed in rows and columns, and    wherein said control means transmits ROW/COL data to said test circuit controlling whether the test circuit tests all cells of a row before testing cells of a next row, or tests all cells of a column before testing cells of a next column.    
     
     
         11 . The apparatus in accordance with  claim 1  further comprising: 
 a scan register ( 46 ) implemented within said IC, and  
 a scan bus ( 23 ) linking said scan register to said control means,  
 wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus,  
 wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         12 . The apparatus in accordance with  claim 1  further comprising: 
 a scan register ( 46 ) implemented within said IC, and  
 a scan bus ( 23 ) linking said scan register to said control means,  
 wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,  
 wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and  
 wherein said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         13 . The apparatus in accordance with  claim 1  further comprising: 
 a scan register ( 46 ) implemented within said IC, and  
 a scan bus ( 23 ) linking said scan register to said control means,  
 wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus,  
 wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         14 . The apparatus in accordance with  claim 1  further comprising: 
 a scan register ( 46 ) implemented within said IC, and  
 a scan bus ( 23 ) linking said scan register to said control means,  
 wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,  
 wherein said scan register stores said RESULT data and data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus, and  
 wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         15 . The apparatus in accordance with  claim 1  wherein said control means comprises an integrated circuit tester external to said IC.  
     
     
         16 . The apparatus in accordance with  claim 1  further comprising a load board ( 66 ) for holding said IC, wherein said control means comprises a built-off self test (BOST) circuit external to said IC mounted on said load board.  
     
     
         17 . The apparatus in accordance with  claim 1  wherein said control means is implemented within said IC.  
     
     
         18 . The apparatus in accordance with  claim 1  further comprising: 
 a scan register ( 46 ) implemented within said IC,  
 a scan bus ( 23 ) linking said scan register to said control means, wherein said control means stores SCAN_INSERT data in said scan register via said scan bus, and  
 multiplexing means ( 48 ) connected to said scan bus for responding to a FORCE signal supplied by said control means via said scan bus by disconnecting a data output port (DO) of said memory from said logic circuit and supplying said SCAN_INSERT data stored in said scan register to said logic circuit.  
 
     
     
         19 . The apparatus in accordance with  claim 1  further comprising switch means ( 42 - 44 ) included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memory and by connecting said test circuit to said memory so that said test circuit can test the memory cells of said memory, 
 wherein said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective,  
 wherein said test circuit continuously asserts an output FAIL signal after determining that any one of said memory cells is defective,  
 wherein said control means supplies a DIAG signal to said test circuit to tell it test said memory in a bit map mode,  
 wherein when said test circuit tests said memory other than in said bit map mode, it asserts a DONE signal when it has completed testing all memory cells of said memory,  
 wherein when said test circuit tests said memory in said bit map mode it pulses said DONE signal when it completes testing any one memory cell of said memory and waits until it receives a READY signal from said control means before testing a next memory cell of said memory,  
 wherein said control means monitors said DONE signal to determine when said test circuit has completed a test.  
 
     
     
         20 . The apparatus in accordance with  claim 19  wherein said control means comprises: 
 means internal to said IC for generating and supplying said MIN, MAX data and said DIAG signal to said test circuit, and  
 means external to said IC for generating said READY signal and for monitoring said CERR, FAIL and DIAG signals.  
 
     
     
         21 . The apparatus in accordance with  claim 19  wherein said control means comprises: 
 a load board ( 66 ) for holding said IC, and  
 a built-off self test (BOST) circuit external to said IC mounted on said load board for generating and supplying said MIN, MAX data and said MODE, DIAG and READY signals to said test circuit and for monitoring said CERR, FAIL and DIAG signals.  
 
     
     
         22 . The apparatus in accordance with  claim 19  wherein said control means comprises: 
 a load board ( 66 ) for holding said IC, and  
 a built-off self test (BOST) circuit external to said IC mounted on said load board for generating and supplying said MIN, MAX data and said MODE and DIAG signals to said test circuit, and  
 means external to said load board for generating said READY signal and for monitoring said CERR, FAIL and DIAG signals.  
 
     
     
         23 . The apparatus in accordance with  claim 19  wherein said control means comprises: 
 a load board ( 66 ) for holding said IC,  
 a built-off self test (BOST) circuit external to said IC mounted on said load board for generating and supplying said READY signal to said test circuit and for generating said READY signal and for monitoring said CERR, FAIL and DIAG signals, and  
 means internal to said IC for generating and supplying said MIN, MAX data and said MODE and DIAG signals to said test circuit.  
 
     
     
         24 . The apparatus in accordance with  claim 19  further comprising: 
 a scan register ( 46 ) implemented within said IC, and  
 a scan bus ( 23 ) linking said scan register to said control means,  
 wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied to said scan register by said control means via said scan bus,  
 wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus, and  
 wherein when the test circuit tests said memory in the bit map mode, said control means supplies said CAPTURE signal to said shift register and pulses said SHIFT signal in response to said DONE signal so that said scan register shifts out it stored data to said control means, said control means thereafter supplying said READY signal to said test circuit.  
 
     
     
         25 . The apparatus in accordance with  claim 24  wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell, 
 wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and  
 wherein said scan register also shifts out its stored RESULT data to said control means via said scan bus in response to pulses of said SHIFT signal.  
 
     
     
         26 . The apparatus in accordance with  claim 25  further comprising multiplexing means ( 48 ) connected to said scan bus for responding to a FORCE signal supplied thereto by said control means via said scan bus by disconnecting a data output port (DO) of said memory from said logic circuit and supplying to said logic circuit said SCAN_INSERT data said control means stores in said scan register via said scan bus.  
     
     
         27 . An apparatus for testing a memory embedded in an integrated circuit (IC), wherein said memory ( 12 ) includes a plurality of addressable memory cells and wherein said IC includes a logic circuit ( 14 , 16 ) linked to said memory for read and write accessing said memory, the apparatus comprising: 
 a test circuit ( 40 ) included in said IC for successively testing all memory cells of said memory, pulsing an output CERR signal whenever it determines one of said memory cells is defective, and continuously asserting an output FAIL signal after determining that any one of said memory cells is defective, and wherein in response to a state of an input DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells; and    a control means for supplying said DIAG signal to said test circuit and for monitoring said DONE signal to determine when said test circuit has completed a test.    
     
     
         28 . The apparatus in accordance with  claim 27  further comprising: 
 a scan register ( 46 ) implemented within said IC, and  
 a scan bus ( 23 ) linking said scan register to said control means,  
 wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus,  
 wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         29 . The apparatus in accordance with  claim 28   wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,    wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and    wherein said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.    
     
     
         30 . An apparatus for testing a plurality of memories embedded in an integrated circuit (IC), wherein each of said memories ( 12 ) includes a plurality of addressable memory cells, wherein at least two of said memories have differing address ranges, and wherein said IC includes logic circuits ( 14 , 16 ) linked to said memories for read and write accessing said memories, the apparatus comprising: 
 a plurality of test circuits ( 40 ) included in said IC, each corresponding to a separate one of said memories, for successively testing all memory cells of the corresponding memory having addresses within the corresponding memory's range of addresses as indicated by input MIN, MAX data to determine whether each memory cell is defective, and    control means ( 21 ,  66  or  68  and  55 ) for supplying said input MIN, MAX data to each of said test circuits.    
     
     
         31 . The apparatus in accordance with  claim 30  further comprising switch means ( 42 - 44 ) included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memories and by connecting each said test circuit to its corresponding memory so that said test circuit can test the memory cells of its corresponding memory, 
 wherein said control means also supplies said MODE control signal to said switch means.  
 
     
     
         32 . The apparatus in accordance with  claim 31   wherein each said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective and continuously asserts an output FAIL signal after determining that any one of said memory cells is defective.    wherein said control means supplies a DIAG signal to each said test circuit, and    wherein in response to a state of said DIAG signal, each said test circuit selectively either asserts an output DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells.    
     
     
         33 . The apparatus in accordance with  claim 32  further comprising a glue logic circuit ( 33 ) for processing output DONE signals of all of said test circuits to provide a single DONEX signal provided as input to said control means, for processing output FAIL signals of all of said test circuits to produce a single FAILX signal provided as input to said control means, and for delivering one of said output CERR signals of said test circuits as input to said control means.  
     
     
         34 . The apparatus in accordance with  claim 30  further comprising: 
 a plurality of scan registers ( 46 ) implemented within said IC, each corresponding to a separate one of said embedded memories, and  
 a scan bus ( 23 ) linking each scan register to said control means,  
 wherein each said scan register stores data appearing at input and output ports of its corresponding memory in response to an input CAPTURE signal supplied by said control means via said scan bus,  
 wherein each said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         35 . The apparatus in accordance with  claim 34  wherein each said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell, 
 wherein each said scan register stores its input RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and  
 wherein each said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         36 . The apparatus in accordance with  claim 30  wherein said control means comprises an integrated circuit tester external to said IC.  
     
     
         37 . The apparatus in accordance with  claim 30  further comprising a load board ( 66 ) for holding said IC, wherein said control means comprises a built-off self test (BOST) circuit external to said IC mounted on said load board.  
     
     
         38 . The apparatus in accordance with  claim 30  wherein said control means is implemented within said IC.  
     
     
         39 . The apparatus in accordance with  claim 35  further comprising multiplexing means ( 48 ) corresponding to each of said memories for responding to a FORCE signal supplied by said control means via said scan bus by disconnecting a data output port (DO) of its corresponding memory from said logic circuit and supplying SCAN_INSERT data stored in said scan register to said logic circuit, 
 wherein said control means stores SCAN_INSERT data in said scan register via said scan bus.  
 
     
     
         40 . An apparatus for testing a plurality of memories embedded in an integrated circuit (IC), wherein each memory ( 12 ) includes a plurality of addressable memory cells and wherein said IC includes logic circuits ( 14 , 16 ) linked to said memory for read and write accessing said memory, the apparatus comprising: 
 a plurality of test circuits( 40 ) included in said IC, each corresponding to a separate one of said Memories, for successively testing all memory cells of the corresponding memory, pulsing an output CERR signal whenever it determines one of said memory cells is defective, and continuously asserting an output FAIL signal after determining that any one of said memory cells is defective, and wherein in response to a state of an input DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells;    glue logic means ( 33 ) for processing the DONE signal output of all of said test circuits to produce a single DONEX output signal, for processing the CERR output signals of all of said test circuits to produce a single CERRX output signal, and for processing the FAIL output signals of all of said test circuits to produce a single FAILX output signal,    control means for supplying said DIAG signal to said test circuit and for monitoring said CERRX, FAILX and DONEX.    
     
     
         41 . The apparatus in accordance with  claim 40  further comprising: 
 a plurality of scan register ( 46 ) implemented within said IC, each scan register corresponding to a separate one of said memories, and  
 a scan bus ( 23 ) linking said scan registers to said control means,  
 wherein each test circuit generates RESULT data after testing any memory cell its corresponding memory, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,  
 wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and  
 wherein said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.  
 
     
     
         42 . The apparatus in accordance with  claim 41  wherein each scan register stores also data appearing at input and output ports of its corresponding memory in response to said CAPTURE signal.  
     
     
         43 . A method of developing a BIST circuit for testing an embedded circuit on a production chip, comprising: 
 providing a development chip including an on-chip circuit configured as the embedded circuit and connections coupling the on-chip circuit to contact points; and    modifying an off-chip circuit external to said development chip and coupled to said contact points, to define said BIST circuit to be included on said production chip.    
     
     
         44 . A method of developing a BIST controller circuit for controlling a BIST circuit when testing an embedded circuit on a production chip, comprising: 
 providing a development chip including an on-chip circuit configured as the embedded circuit, a BIST circuit for testing said on-chip circuit, and connections for coupling the BIST circuit to contact points; and    modifying an off-chip circuit external to said development chip coupled to said contact points to define said BIST controller circuit to be included on said production chip.    
     
     
         45 . A method of developing a production chip including an embedded circuit and a BIST circuit connected to said embedded circuit for performing a test on the embedded circuit, the method comprising the steps of: 
 providing a development chip including said embedded circuit and connections coupling the embedded circuit to contact points;    providing an off-chip circuit external to said development chip and coupled to said contact points,    modifying said off-chip circuit so that it performs said test on said embedded circuit; and    defining said production chip including said embedded circuit and said BIST circuit, wherein said BIST circuit incorporates elements of the off-chip circuit as modified.    
     
     
         46 . A method of developing a production chip including an embedded circuit, a BIST controller, and a BIST circuit, said BIST circuit being connected coupled to said embedded circuit and to said BIST controller for performing a test on the embedded circuit under control of said BIST controller, the method comprising the steps of: 
 providing a development chip including said embedded circuit, said BIST circuit coupled to said embedded circuit, and connections coupling the BIST circuit to contact points;    providing an off-chip circuit external to said development chip and coupled to said contact points,    modifying said off-chip circuit so that it appropriately controls said BIST circuit to perform said test on said embedded circuit; and    defining said production chip including said embedded circuit, said BIST circuit and said BIST controller, wherein said BIST controller incorporates elements of said off-chip circuit as modified.    
     
     
         47 . A method of developing a production chip including an embedded circuit and a BIST circuit connected to said embedded circuit for performing a test on the embedded circuit, the method comprising the steps of: 
 producing a development chip including said embedded circuit and connections coupling the embedded circuit to contact points;    providing an off-chip circuit external to said development chip and coupled to said contact points;    modifying said off-chip circuit so that it performs said test on said embedded circuit; and    producing said production chip including said embedded circuit and said BIST circuit, wherein said BIST circuit incorporates elements of the off-chip circuit as modified.    
     
     
         48 . A method of developing a production chip including an embedded circuit, a BIST controller, and a BIST circuit, said BIST circuit being connected to said embedded circuit and to said BIST controller for performing a test on the embedded circuit under control of said BIST controller, the method comprising the steps of: 
 producing a development chip including said embedded circuit, said BIST circuit connected to said embedded circuit, and connections coupling the BIST circuit to contact points;    providing an off-chip circuit external to said development chip and coupled to said contact points;    modifying said off-chip circuit so that it controls said BIST circuit in performing said test on said embedded circuit; and    producing said production chip including said embedded circuit, said BIST circuit and said BIST controller, wherein said BIST controller incorporates elements of said off-chip circuit as modified.