Dynamic random access memory with improved contact arrangements

Abstract

A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.

What is claimed is:  
     
         1  A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: 
 (a) forming first MISFETs for selecting memory cells and a first insulation film for covering the, first MISFETs, and etching the first insulation film in order to have openings on at least one of the source/drain regions of each of the first MISFETs;  
 (b) depositing a polycrystal silicon film on the surface of the semiconductor substrate to fill the openings of the first insulation film and forming polycrystal silicon plugs electrically connected to the source/drain regions of the first MISFETs by removing the polycrystal silicon film on the first insulation film;  
 (c) forming a second insulation film on the first insulation film and then forming first contact holes in the second insulation film by etching the second insulation film in order to expose the surface of polycrystal silicon plugs;  
 (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and one or more than one impurities selected from nitrogen, oxygen, carbon and germanium, or a cobalt film containing no impurity on the bottom of the first contact holes and on the second insulation film, and then heat-treating the metal film;  
 (e) depositing a first electro-conductive film on the metal film or the cobalt film, whichever appropriate, to fill the first contact holes; and  
 (f) forming bit lines by etching the first electro-conductive film and the metal film or the cobalt film.  
 
     
     
         2 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein the silicide film formed by the heat treatment in the contact areas of the metal film or the cobalt film, whichever appropriate, operates as etching stopper in the subsequent etching step.  
     
     
         3 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein the pattern width of each bit lines is not greater than the bore of the first contact holes.  
     
     
         4 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein 
 the impurity concentration of the metal film is between 1atomic % and 13atomic %.    
     
     
         5 . A method of manufacturing a semiconductor integrated circuit device according to  claim 4 , wherein 
 the impurity is nitrogen and the nitrogen concentration of the metal film is between 1 atomic % and 3atomic %.    
     
     
         6 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein 
 the first conductive-conductive film is a laminate film having a titanium nitride layer and a tungsten layer.    
     
     
         7 . A method of manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein 
 second MISFETs for peripheral circuits are formed in the step of forming the first MISFETs;    second contact holes for electrically connecting to the source/drain regions or the gate electrodes of the second MISFETs or the principal surface of the semiconductor substrate are formed in the step of forming the first contact holes or immediately before or after the step of forming the first contact holes;    a first wiring layer for peripheral circuits is formed in the step of forming the bit lines.    
     
     
         8 . A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: 
 (a) forming first MISFETs for selecting memory cells and a first insulation film for covering the first MISFETs, and etching the first insulation film in order to have openings on at least one of the source/drain regions of each of the first MISFETs;    (b) depositing a polycrystal silicon film on the surface of the semiconductor substrate to fill the openings of the first insulation film and forming polycrystal silicon plugs electrically connected to the source/drain regions of the first MISFETs by removing the polycrystal silicon film on the first insulation film;    (c) forming a second insulation film on the first insulation film and then forming first contact holes in the second insulation film by etching the second, insulation film in order to expose the surface of polycrystal silicon plugs;    (d) depositing a first conductive-conductive film to fill the first contact holes and forming first plugs made of the first conductive-conductive film in the first contact holes by removing the first electro-conductive film on the second insulation film;    (e) depositing a second electro-conductive film on the first plugs and the second insulation film; and    (f) patterning the second conductive-conductive film to produce bit lines.    
     
     
         9 . A method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein 
 the first insulation film is planarized by means of a CMP technique before the step of etching the first insulation film; and    the first plugs are formed by polishing the first electro-conductive film by means of a CMP technique.    
     
     
         10 . A method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein 
 the film thickness of the second electro-conductive film is not greater than the bore of the first contact holes.    
     
     
         11 . A method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein 
 the width of the bit lines is not greater than the bare of the first contact holes.    
     
     
         12 . A method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein the second electro-conductive film is made of a material having an etching selectivity relative to the first plugs.  
     
     
         13 . A method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein 
 the first conductive-conductive film is a laminate film including a titanium nitride film and a tungsten film or a single layer film of titanium nitride or tungsten nitride; and    the second electro-conductive film is a single layer film of tungsten or molybdenum.    
     
     
         14 . A method of manufacturing a semiconductor integrated circuit device according to  claim 8 , wherein 
 second MISFETs are formed for peripheral circuits in the step of forming the first MISFETs; and    second contact holes for electrically connecting to the source/drain regions of the second MISFETs are formed in the step of forming the first contact hales or immediately before or after the step of forming the first contact holes;    second plugs made of the first conductive-conductive film are farmed in the second contact holes in the step of forming the first plugs; and    a first wiring layer made of the second electro-conductive film is formed for peripheral circuits in the step of forming the bit lines.    
     
     
         15 . A method of manufacturing a semiconductor integrated circuit device according to  claim 14 , wherein it further comprises; 
 a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and one or more than one impurities selected from nitrogen, oxygen, carbon and germanium to a concentration between 1atomic % and 13atomic % or a cobalt film containing no impurity on the bottom of the first and second contact holes and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.    
     
     
         16 . A method of manufacturing a semiconductor integrated circuit device according to  claim 14 , wherein it further comprises: 
 a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient to a film thickness between 10 and 20 nm on the bottom of the first and second contact holes and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.    
     
     
         17 . A method of manufacturing a semiconductor integrated circuit device according to  claim 14 , wherein it further comprises: 
 a step of depositing a film of silicide of titanium, tungsten or cobalt to a film thickness between 15 and 30 nm on the bottom of the first and second contact holes and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.    
     
     
         18 . A method of manufacturing a semiconductor integrated circuit device according to  claim 14 , wherein it further comprises: 
 a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and then a silicon film having a film thickness smaller than that of the metal film on the bottom of the first and second contact hales and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.    
     
     
         19 . A method of manufacturing a semiconductor integrated circuit device according to  claim 14 , wherein it further comprises: 
 a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient on the bottom of the first and second contact holes and on the second insulation film, and annealing the metal film in an atmosphere of silicon hydride gas before forming the first and second plugs.    
     
     
         20 . A method of manufacturing a semiconductor integrated circuit device according to claim,  16 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.    
     
     
         21 . A method of manufacturing a semiconductor integrated circuit device according to  claim 17 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.    
     
     
         22 . A method of manufacturing a semiconductor integrated circuit device according to  claim 18 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.    
     
     
         23 . A method of manufacturing a semiconductor integrated circuit device according to  claim 19 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.    
     
     
         24 . A method of manufacturing a semiconductor integrated circuit device comprising the steps of: 
 (a) forming MISFETs an the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs;    (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs;    (c) depositing an conductive-conductive film to fill the openings, forming wires; and    (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient to a film thickness between 10 and 20 nm on the bottom of the contact holes and on the insulation film prior to farming said conductive-conductive film, and heat-treating it.    
     
     
         25 . A method of manufacturing a semiconductor integrated circuit device comprising the steps of: 
 (a) forming MISFETs on the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs;    (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs;    (c) depositing an conductive-conductive film to fill the openings, forming wires; and    (d) depositing a film of silicide of titanium, tungsten or cobalt to a film thickness between 15 and 30 nm on the bottom of the contact holes and on the insulation film prior to forming said conductive-conductive film.    
     
     
         26 . A method of manufacturing a semiconductor integrated circuit device comprising the steps of: 
 (a) farming MISFETs on the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs;    (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs;    (c) depositing an conductive-conductive film to fill the openings, forming wires; and    (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and then a silicon film having a film thickness smaller than that of the metal film on the bottom of the contact holes and on the insulation film prior to forming said conductive-conductive film, and heat-treating them.    
     
     
         27 . A method of manufacturing a semiconductor integrated circuit device comprising the steps of: 
 (a) forming MISFETs on the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs;    (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs;    (c) depositing an conductive-conductive film to fill the openings, forming wires; and    (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient on the bottom of the contact holes and an the insulation film, and annealing the metal film in an atmosphere of silicon hydride gas prior to forming said conductive-conductive film.    
     
     
         28 . A method of manufacturing a semiconductor integrated circuit device according to  claim 24 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-p treating the metal film.    
     
     
         29 . A method of manufacturing a semiconductor integrated circuit device according to  claim 14 , wherein 
 the conductive-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of titanium, titanium nitride and tungsten.    
     
     
         30 . A method of manufacturing a semiconductor integrated circuit device according to  claim 25 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.    
     
     
         31 . A method of manufacturing a semiconductor integrated circuit device according to  claim 25 , wherein 
 the conductive-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of titanium, titanium nitride and tungsten.    
     
     
         32 . A method of manufacturing a semiconductor integrated circuit device according to  claim 26 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.    
     
     
         33 . A method of manufacturing a semiconductor integrated circuit device according to  claim 26 , wherein. 
 the conductive-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of titanium, titanium nitride and tungsten.    
     
     
         34 . A method of manufacturing a semiconductor integrated circuit device according to  claim 27 , wherein 
 the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.    
     
     
         35 . A method of manufacturing a semiconductor integrated circuit device according to  claim 27 , wherein 
 the conductive-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of titanium, titanium nitride and tungsten.    
     
     
         36 . A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: 
 (a) forming MISFETs on the principal surface of a semiconductor substrate;    (b) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient to a film thickness between 10 and 20 nm in areas covering at least the source/drain regions of the MISFETs;    (c) heat-treating the metal film to farm a silicide film in areas contacting the silicon;    (d) selectively removing the unreacted titanium, tungsten or cobalt by etching;    (e) forming an insulation film for covering the MISFETs;    (f) etching the insulation film on the source/drain regions of the MISFETs so as to produce contact holes in the insulation film; and    (g) depositing an conductive-conductive film to fill the contact holes, and farming wires.    
     
     
         37 . A method of manufacturing a semiconductor integrated circuit device according to  claim 36 , wherein 
 the conductive-conductive film is a laminate film of titanium nitride and tungsten or a three-layered laminate film of titanium, titanium nitride and tungsten.    
     
     
         38 . A method of a semiconductor integrated circuit device having a first MISFET for a memory cell and a second MISFET far a peripheral circuit, comprising the steps of: 
 (a) forming a first MISFET at a first portion of a semiconductor substrate and a second MISFET at a second portion of said semiconductor substrate;    (b) farming a first insulating film covering said first and second MISFETs;    (c) performing a first etching to said first insulating film in order to farm a first contact hole to expose one of source and drain regions of said first MISFET;    (d) depositing a polycrystal silicon film in said first contact hale and removing said polycrystal silicon film on said first insulating film so as to form a first plug electrode in said first contact hole;    (e) forming a second insulating film aver said first insulating film and said first plug electrode;    (f) performing a second etching to said second insulating film in order to form a second contact hole to expose the surface of said first plug electrode, and performing said second etching to said second and first insulating films in order to form a third contact hole to expose one of source and drain regions of said second MISFET;    (g) depositing a first metal film in said second and third contact holes in order to fill said second and third contact holes, and etching said first metal film on said second insulating film and leaving said first metal film into said second and third contact holes so as to farm a second plug electrode in said second contact hole and a third plug electrode in said third contact hale; and    (h) depositing a second metal film over said second insulating film and patterning said second metal film in order to farm a bit line conductor electrically connected to said second plug electrode and a wiring conductor electrically connected to said third plug electrode.    
     
     
         39 . A method of manufacturing a semiconductor integrated circuit device having a DRAM comprising the steps of: 
 (a) forming a MISFET for selecting a memory cell of said DRAM at a principal surface of a semiconductor substrate;    (b) forming a first insulating film over said MISFET;    (c) forming a first opening in the first insulating film reaching the principal surface of said semiconductor substrate;    (d) forming a first conductor in said first opening, electrically connected to a source or drain region of said MISFET;    (e) forming a second insulating film over said first conductor;    (f) forming a second opening in said second insulating film;    (g) forming a second conductor in said second opening, electrically connected to said first conductor; and    (h) forming a bit line of said memory cell on said second conductor, electrically connected to said second conductor,    wherein said first conductor and second conductor are comprised of different materials.    
     
     
         40 . A method of manufacturing a semiconductor integrated circuit device according to  claim 39 , wherein 
 said first conductor is comprised of polycrystalline silicon; and    said second conductor and bit line are comprised of tungsten.    
     
     
         41 . A method of manufacturing a semiconductor integrated circuit device according to  claim 39 , between said steps (f) and (g), further comprising the steps of: 
 (i) forming a titanium silicide film in said second opening; and    (j) forming a titanium nitride film over said titanium silicide film.    
     
     
         42 . A method of manufacturing a semiconductor integrated circuit device according to  claim 39 , wherein a capacitor of said memory cell is formed over said bit line.  
     
     
         43 . A method of manufacturing a semiconductor integrated circuit device having a DRAM comprising the steps of: 
 (a) forming a MISFET for selecting a memory cell of said DRAM at a principal surface of a semiconductor substrate:    (b) forming a first insulating film over said MISFET;    (c) forming first and second openings in said first insulating film reaching the principal surface of said semiconductor substrate;    (d) forming first and second conductors in said first and second openings respectively, wherein said first and second conductors are electrically connected to a source or drain region of said MISFET;    (e) forming a second insulating film over said first and second conductors;    (f) forming a third opening in said second insulating film;    (g) forming a third conductor in said third opening, wherein said third conductor is electrically connected to said first conductor;    (h) forming a bit line of said memory cell on said third conductor, wherein said bit line is electrically connected to said third conductor;    (i) forming a third insulating film over said bit line;    (j) forming a fourth opening in said second and third insulating film;    (k) forming a fourth conductor in said fourth opening, wherein said fourth conductor and second conductor are electrically connected to said fourth conductor, and    wherein said first conductor and third conductor are comprised of different materials.