Architecture and design of universal IC test system

Abstract

A universal IC test system is designed to function both an event tester and a cyclized tester. The universal test system is comprised of an event tester for testing DUT by test vectors produced based on event data derived directly from simulation of design data of DUT produced in an EDA environment a cyclized tester for testing DUT by test vectors produced based on test data formulated in a cyclized format in which each test vector is defined by a waveform, a test rate, and a timing with respect to the test rate, a pin-electronics for applying the test vector to DUT and comparing a response output of DUT, and means for changing a tester mode between an event tester mode and a cyclized tester mode thereby testing DUT either by the event tester or the cyclized tester, or by both testers.

What is claimed is:  
     
         1 . A universal test system for testing an IC device under test (DUT), comprising: 
 an event tester for testing DUT by test vectors produced based on event data derived directly from simulation of design data of DUT produced in an EDA (electronic design automation) environment wherein each event in the event data is defined by an event time indicating a time length of the event from a predetermined point and an event type indicating a type of change at the event;    a cyclized tester for testing DUT by test vectors produced based on test data formulated in a cyclized format in which each test vector is defined by a waveform, a test rate, and a timing with respect to the test rate;    a pin-electronics for applying the test vector to DUT and comparing a response output of DUT; and    means for changing a tester mode between an event tester mode and a cyclized tester mode thereby testing DUT either by the event tester or the cyclized tester, or by both the event tester and the cyclized tester.    
     
     
         2 . A universal test system as defined in  claim 1 , wherein the event tester is comprised of: 
 an event memory for storing the event data which defines the event time and the event type of each event;    an event generator for generating the test vectors based on the event data from the event memory;    and wherein the cyclized tester is comprised of: 
 a rate generator for producing the test rate;  
 at least one memory for storing pattern data, timing data, and waveform data;  
 a timing generator for producing timing signals based on the timing data; and  
 a waveform formatter for producing the test vectors based on the timing signals, pattern data and waveform data.  
   
     
     
         3 . A universal test system as defined in  claim 1 , wherein the event time in the event tester is defined by an integer multiple of a reference clock period (integral part data) and a fraction of the reference clock period (fractional part data).  
     
     
         4 . A universal test system as defined in  claim 2 , wherein the predetermined point for defining the time length by the event time is an event immediately prior to a current event so that the event time expresses a delta time between two adjacent events.  
     
     
         5 . A universal test system as defined in  claim 2 , wherein the predetermined point for defining the time length by the event time is a start point of operation so that the event time expresses an absolute time of the event.  
     
     
         6 . A universal test system as defined in  claim 2 , wherein the means for changing the tester mode includes a relay to switch a pair of a driver and a comparator in the pin-electronics.  
     
     
         7 . A universal test system as defined in  claim 2 , wherein the means for changing the tester mode includes relays to independently switch a driver and a comparator in the pin-electronics so that one test channel of the universal test system tests two pins of DUT.  
     
     
         8 . A universal test system as defined in  claim 1 , comprising: 
 a memory for storing the event data for use with the event tester and the test data for use with the cyclized tester;    a memory controller for managing operations of the memory depending on whether the DUT is tested by the event tester mode or the cyclized tester mode;    an event generator for generating the test vectors based on the event data from the memory;    a rate generator for producing the test rate in the cyclized tester mode;    a timing generator for producing timing signals based on the timing data in the cyclized tester mode;    a waveform formatter for producing the test vectors based on the timing signals, pattern data and waveform data in the cyclized tester mode; and    means for selecting the test vectors from the event generator or the waveform formatter to apply the test vectors to DUT.    
     
     
         9 . A universal test system for testing an IC device under test (DUT), comprising: 
 a host computer for controlling an overall operation of the universal test system;    a plurality of tester modules for generating test vectors and supplying the test vectors to DUT and evaluating response outputs of the DUT;    wherein one of the tester modules is configured by a combination of an event tester and a cyclized tester where the event tester tests DUT by test vectors produced based on event data derived directly from simulation of design data of DUT produced in an EDA (electronic design automation) environment and the cyclized tester tests DUT by test vectors produced based on test data formulated in a cyclized format in which each test vector is defined by a waveform, a test rate, and a timing with respect to the test rate.    
     
     
         10 . A universal test system as defined in  claim 9 . wherein at least one of the tester modules is configured solely by the event tester and at least another one of the tester modules is configured solely by the cyclized tester.  
     
     
         11 . A universal test system as defined in  claim 9 , where at least one of the tester modules is configured a universal type tester which can operate either in an event form or in a cyclized form.  
     
     
         12 . A universal test system for testing an IC device under test (DUT), comprising: 
 a host computer for controlling an overall operation of the universal test system;    interface software for interfacing the host computer and the universal test system, the interface software including graphic user interface (GUI) establishing an input means, command control and viewer for monitoring and editing test vectors for the universal test system;    data interpretation and management software for interpreting and managing data from the host computer through the interface software; and    universal test system hardware having an event tester mode for testing DUT by test vectors produced based on event data derived directly from simulation of design data of DUT produced in an EDA (electronic design automation) environment and a cyclized tester mode for testing DUT by test vectors produced based on test data formulated in a cyclized format in which each test vector is defined by waveform, a test rate, and a timing with respect to the test rate.    
     
     
         13 . A universal test system as defined in  claim 12 , wherein the interface software and the data interpretation and management software communicate directly or through a public communication network or a dedicated communication network.  
     
     
         14 . A universal test system as defined in  claim 12 , wherein the data interpretation and management software includes middleware for data processing and interpretation, and kernel for mediating data values between the event tester hardware and the middleware.  
     
     
         15 . A universal test system as defined in  claim 12 , wherein the middleware interprets information specified by a user and produces data including types of test, an order of tests and test parameters for supplying the data to the event tester hardware through the kernel.  
     
     
         16 . A universal test system as defined in  claim 12 , wherein the middleware interprets information specified by a user and produces data including I/O pin and power supply pin of DUT in addition to types of test, order of tests and test parameters for supplying the data to the universal test system hardware through the kernel.