SOI structure having a SiGe Layer interposed between the silicon and the insulator

Abstract

A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

1 . A semiconductor structure comprising: 
 an insulator configured to provide electrical isolation;    a silicon germanium layer in direct contact with said insulator; and    a silicon layer in contact with said silicon germanium layer, said silicon layer having a higher band gap than said silicon germanium layer.    
     
     
         2 . The structure of  claim 1 , wherein said silicon germanium layer is configured to receive minority carriers from the silicon layer to minimize charge accumulation in the silicon layer.  
     
     
         3 . The structure of  claim 1 , further comprising: 
 a semiconductor substrate; and    said insulator comprising an insulating layer formed on said semiconductor substrate.    
     
     
         4 . The structure of  claim 3 , wherein the insulating layer comprises SiO 2 .  
     
     
         5 . The structure of  claim 3 , wherein the semiconductor comprises a silicon wafer.  
     
     
         6 . The structure of  claim 1 , wherein the insulator comprises at least one of a glass substrate, a quartz substrate, and a sapphire substrate.  
     
     
         7 . The structure of  claim 1 , wherein the silicon germanium layer has a germanium concentration of 5 to 30%.  
     
     
         8 . The structure of  claim 7 , wherein the germanium concentration ranges from 10-25%.  
     
     
         9 . The structure of  claim 1 , wherein the silicon germanium layer comprises an epitaxial silicon germanium layer grown initially on a separate substrate.  
     
     
         10 . The structure of  claim 9 , wherein the silicon layer comprises an epitaxial silicon layer grown on said epitaxial silicon germanium layer.  
     
     
         11 . The structure of  claim 1 , wherein the silicon germanium layer has a thickness ranging from 20 to 50 nm.  
     
     
         12 . The structure of  claim 1 , wherein the silicon layer has a thickness ranging from 100 to 200 nm.  
     
     
         13 . The structure of  claim 1 , further comprising: 
 a drain formed in at least the silicon layer;    a source formed in at least the silicon layer;    a gate insulator formed above said silicon layer; and    a gate electrode formed above said gate insulator, said gate electrode configured to control an active region between said source and said drain.    
     
     
         14 . The structure of  claim 13 , wherein the silicon germanium layer is configured to receive minority carriers from the silicon layer to minimize charge accumulation in the silicon layer.  
     
     
         15 . The structure of  claim 13 , wherein the silicon germanium layer is configured to conduct said minority carriers to said drain.  
     
     
         16 . A method of manufacturing a silicon on insulator SOI wafer having a silicon germanium SiGe layer in contact with said insulator, comprising: 
 epitaxially growing a first SiGe layer, a silicon layer, and a second SiGe layer in sequence on a first substrate;    forming an insulating layer on the second SiGe layer;    implanting impurity ions into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region;    bonding a second substrate to the insulating layer on the first substrate; and    separating the first substrate along the impurity implantation region and removing the first substrate.    
     
     
         17 . The method of  claim 16 , further comprising: 
 removing the first SiGe layer remaining on a surface of a separated region of the second substrate so that the surface of the silicon layer is exposed.    
     
     
         18 . The method of  claim 17 , further comprising: 
 annealing the second substrate in an hydrogen atmosphere after removal of the remaining first SiGe layer.    
     
     
         19 . The method of  claim 16 , wherein the epitaxially growing comprises epitaxially growing on a silicon substrate.  
     
     
         20 . The method of  claim 16 , wherein the epitaxially growing the first SiGe layer comprises: 
 epitaxially growing the first SiGe layer to a thickness of 10-50 Å.    
     
     
         21 . The method of  claim 16 , wherein the forming an insulating layer comprises: 
 forming a silicon oxide layer.    
     
     
         22 . The method of  claim 16 , wherein the implanting impurity ions comprises: 
 implanting hydrogen impurity ions.    
     
     
         23 . The method of  claim 16 , wherein the implanting impurity ions comprises: 
 implanting the impurity ions below the first SiGe layer.    
     
     
         24 . The method of  claim 16 , wherein the implanting impurity ions comprises: 
 implanting the impurity ions at a depth of 50-100 Å below the first SiGe layer.    
     
     
         25 . The method of  claim 16 , further comprising: 
 annealing the second substrate after separation of the first substrate.    
     
     
         26 . The method of  claim 16 , wherein the annealing comprises: 
 annealing the second substrate at a temperature above 1,100° C. for a time in a range of 1 to 2 hours after separation of the first substrate.    
     
     
         27 . A method of manufacturing a silicon on insulator (SOI) wafer having a silicon germanium (SiGe) layer, comprising: 
 epitaxially growing the SiGe layer and a silicon layer in sequence on a substrate;    forming an insulating layer on the silicon layer;    implanting impurity ions into a predetermined location of the substrate underlying the SiGe layer to form an impurity implantation region;    annealing the substrate; and    thermally oxidizing the impurity implantation region to form said insulator of said SOI wafer.    
     
     
         28 . The method of  claim 27 , further comprising: 
 removing said insulating layer formed on a topmost surface of the substrate.    
     
     
         29 . The method of  claim 27 , wherein the epitaxially growing comprises: 
 epitaxially growing the SiGe layer on a silicon substrate.    
     
     
         30 . The method of  claim 27 , wherein the epitaxially growing comprises: 
 epitaxially growing the SiGe layer to a thickness of 200-300 Å.    
     
     
         31 . The method of  claim 27 , wherein the implanting comprises: 
 implanting at least oxygen impurity ions.    
     
     
         32 . The method of  claim 27 , wherein the forming an insulating layer comprises: 
 forming a silicon oxide layer.    
     
     
         33 . The method of  claim 27 , wherein the implanting impurity ions comprises: 
 implanting the impurity ions below the SiGe layer.    
     
     
         34 . The method of  claim 33 , wherein the implanting impurity ions comprises: 
 implanting the impurity ions implanted at a depth 400-600 Å from below the SiGe layer.    
     
     
         35 . The method of  claim 27 , wherein the annealing comprises: 
 annealing at a temperature above 1,300° C. in an argon atmosphere containing less than 1% oxygen.    
     
     
         36 . The method of  claim 27 , wherein the annealing comprises: 
 oxidizing at a temperature above 1,300° C. in an argon atmosphere containing greater than 50% oxygen.    
     
     
         37 . A method of manufacturing a silicon on insulator (SOI) wafer having a silicon germanium (SiGe) layer thereon, comprising: 
 forming a porous silicon layer on a first substrate;    epitaxially growing a silicon layer and the SiGe layer in sequence on the porous silicon layer;    forming an insulating layer on the SiGe layer;    bonding a second substrate to the insulating layer on the first substrate to form a bonded first and second substrate;    annealing the bonded first and second substrate;    separating the first substrate from the bonded first and second substrate along the porous silicon layer and removing the first substrate; and    removing remnants of the porous silicon layer.    
     
     
         38 . The method of  claim 37 , wherein the forming a porous silicon layer comprises: 
 performing an anodization of the first substrate.    
     
     
         39 . The method of  claim 37 , wherein the forming an insulating layer comprises: 
 forming a silicon oxide layer.    
     
     
         40 . The method of  claim 37 , wherein the removing remnants comprises: etching the remnants a mixture of 40% HF, 70% HNO 3 , and 98% CH 3 COOH.  
     
     
         41 . The method of  claim 37 , further comprising: 
 annealing the second substrate in a hydrogen atmosphere after removal of the porous silicon layer.