Providing high precision resistance in an integrated circuit using a thin film resistor of controlled dimension

Abstract

In one embodiment, an integrated circuit includes a thin film resistor, which includes a resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the resistor material having an initial width determined by a width of the channel. The stencil structure has been adapted to receive a planarizing material that protects against reduction of the initial width of the resistor material during subsequent process steps for removing the stencil structure. A head mask overlays an end portion of the thin film resistor and a dielectric overlays the head mask, the dielectric defining a via formed in the dielectric above a portion of the head mask. A conductive material has been deposited in the via, coupled to the portion of the head mask and electrically connecting the thin film resistor to other components of the integrated circuit.

What is claimed is:  
     
         1 . An integrated circuit, comprising: 
 a thin film resistor comprising a thin film resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the thin film resistor material having an initial width determined by a width of the channel, the stencil structure having been adapted to receive a planarizing material so as to substantially surround the thin film resistor material within the channel and protect against reduction of the initial width of the thin film resistor material during subsequent process steps for removing the stencil structure from the substrate surface;    a head mask material overlaying an end portion of the thin film resistor;    a dielectric material overlaying the head mask material and defining a via formed in the dielectric material above a portion of the head mask material; and    a conductive material deposited in the via and coupled to the portion of the head mask material, the conductive material electrically connecting the thin film resistor to one or more other components of the integrated circuit.    
     
     
         2 . The integrated circuit of  claim 1 , wherein the thin film resistor has a final width of less than approximately 2 μm.  
     
     
         3 . The integrated circuit of  claim 1 , wherein the thin film resistor has a final width that differs from the initial width of the thin film resistor material by less than approximately 0.1 μm.  
     
     
         4 . The integrated circuit of  claim 1 , wherein the presence of the planarizing material allows the stencil structure to be removed from the substrate surface using standard wet etch techniques while substantially preventing etch-back or undercutting of the thin film resistor material.  
     
     
         5 . The integrated circuit of  claim 1 , wherein each opposing portion of the stencil structure comprises: 
 a first stencil structure layer deposited on the substrate surface; and    a second stencil structure layer deposited on the first stencil structure layer, the second stencil structure layer comprising a different material than the first stencil structure layer, the second stencil structure layer extending further into the channel than the first stencil structure layer due to preferential etching of the first stencil structure layer relative to the second stencil structure layer, the width of the channel between opposing second stencil structure layers determining the initial width of the thin film resistor material.    
     
     
         6 . The integrated circuit of  claim 1 , wherein each opposing portion of the stencil structure comprises a negative resist material and is angled from a top of the channel to a bottom of the channel, the top of the channel being narrower than the bottom of the channel, the width of the channel at the top of the channel determining the initial width of the thin film resistor material.  
     
     
         7 . The integrated circuit of  claim 1 , further comprising a hard mask material covering the end portion of the thin film resistor and underlying the head mask material, the hard mask material having been initially deposited on substantially all of the thin film resistor material within the channel to protect against diffusion of the head mask material into the thin film resistor during operation of the integrated circuit.  
     
     
         8 . The integrated circuit of  claim 7 , wherein: 
 the thin film resistor material has been deposited using first collimated beams comprising the thin film resistor material and directed substantially perpendicular to the substrate surface; and    the hard mask material has been deposited using second collimated beams comprising the hard mask material and directed substantially perpendicular to the substrate surface.    
     
     
         9 . The integrated circuit of  claim 7 , wherein: 
 the thin film resistor material comprises an alloy of nickel and chromium;    the hard mask material comprises an alloy of titanium and tungsten;    the planarizing material comprises at least one of polyimide, a photoresist material, an organic material, a plasma oxide, and an inorganic dielectric; and    the head mask material and the conductive material each comprise at least one of aluminum and copper.    
     
     
         10 . The integrated circuit of  claim 1 , wherein the integrated circuit comprises a high precision analog integrated circuit.  
     
     
         11 . A method for constructing a thin film resistor for an integrated circuit, comprising: 
 forming a stencil structure on a substrate surface, the stencil structure comprising one or more layers and defining a channel separating first and second opposing portions of the stencil structure;    depositing a thin film resistor material, some of the thin film resistor material being deposited on the substrate surface within the channel to define the thin film resistor, some of the thin film resistor material being deposited outside the channel on the first and second opposing portions of the stencil structure, the thin film resistor having an initial width determined by a width of the channel;    depositing a planarizing material within the channel so as to substantially surround the thin film resistor within the channel and protect against reduction of the initial width of the thin film resistor during subsequent process steps for removing the stencil structure from the substrate surface;    removing at least some of the planarizing material sufficient to expose the thin film resistor material deposited outside the channel on the first and second opposing portions of the stencil structure, the thin film resistor within the channel remaining covered by the planarizing material;    removing the thin film resistor material deposited outside the channel on the first and second opposing portions of the stencil structure;    removing the first and second opposing portions of the stencil structure; and    removing the remaining planarizing material deposited on the thin film resistor within the channel.    
     
     
         12 . The method of  claim 11 , wherein the thin film resistor has a final width of less than approximately 2 μm.  
     
     
         13 . The method of  claim 11 , wherein the thin film resistor has a final width that differs from the initial width of the thin film resistor by less than approximately 0.1 μm.  
     
     
         14 . The method of  claim 11 , wherein the presence of the planarizing material allows the stencil structure to be removed from the substrate surface using standard wet etching techniques while substantially preventing etch-back or undercutting of the thin film resistor.  
     
     
         15 . The method of  claim 11 , wherein forming the stencil structure on the substrate surface further comprises: 
 depositing a first stencil structure layer on the substrate surface; and    depositing a second stencil structure layer on the first stencil structure layer, the second stencil structure layer comprising a different material than the first stencil structure layer, the second stencil structure layer extending further into the channel than the first stencil structure layer due to preferential etching of the first stencil structure layer relative to the second stencil structure layer, the width of the channel between opposing second stencil structure layers determining the initial width of the thin film resistor.    
     
     
         16 . The method of  claim 11 , wherein each opposing portion of the stencil structure comprises a negative resist material and is angled from a top of the channel to a bottom of the channel, the top of the channel being wider than the bottom of the channel, the width of the channel at the top of the channel determining the initial width of the thin film resistor.  
     
     
         17 . The method of  claim 11 , further comprising: 
 depositing a head mask material overlaying an end portion of the thin film resistor;    depositing a dielectric material overlaying the head mask material and defining a via formed in the dielectric material above a portion of the head mask material; and    depositing a conductive material in the via and coupled to the portion of the head mask material, the conductive material electrically connecting the thin film resistor to one or more other components of the integrated circuit.    
     
     
         18 . The method of  claim 17 , further comprising: 
 depositing a hard mask material on substantially all of the thin film resistor within the channel to protect against diffusion of the head mask material into the thin film resistor during operation of the integrated circuit; and    removing a portion of the hard mask material such that the hard mask material covers the end portion of the thin film resistor underlying the head mask material.    
     
     
         19 . The method of  claim 18 , wherein: 
 the thin film resistor material is deposited using first collimated beams comprising the thin film resistor material and directed substantially perpendicular to the substrate surface; and    the hard mask material is deposited using second collimated beams comprising the barrier material and directed substantially perpendicular to the substrate surface.    
     
     
         20 . The method of  claim 18 , wherein: 
 the thin film resistor material comprises an alloy of nickel and chromium;    the hard mask material comprises an alloy of titanium and tungsten;    the planarizing material comprises at least one of polyimide, a photoresist material, an organic material, a plasma oxide, and an inorganic dielectric; and    the head mask material and the conductive material comprise at least one of aluminum and copper.    
     
     
         21 . The method of  claim 11 , wherein removing at least some of the planarizing material sufficient to expose the thin film resistor material deposited outside the channel and removing the thin film resistor material deposited outside the channel comprise using a chemical mechanical polishing (CMP) technique.  
     
     
         22 . The method of  claim 11 , wherein the integrated circuit comprises a high precision analog integrated circuit.  
     
     
         23 . An integrated circuit, comprising: 
 a thin film resistor comprising a thin film resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the thin film resistor material having an initial width determined by a width of the channel, the thin film resistor material having been deposited using first collimated beams comprising the thin film resistor material and directed substantially perpendicular to the substrate surface, the stencil structure having been adapted to receive a planarizing material so as to substantially surround the thin film resistor material within the channel and protect against reduction of the initial width of the thin film resistor material during subsequent process steps for removing the stencil structure from the substrate surface, the presence of the planarizing material allowing the stencil structure to be removed from the substrate surface using standard wet etch techniques while substantially preventing etch-back or undercutting of the thin film resistor material;    a head mask material overlaying an end portion of the thin film resistor;    a hard mask material covering the end portion of the thin film resistor and underlying the head mask material, the hard mask material having been initially deposited on substantially all of the thin film resistor material within the channel to protect against diffusion of the head mask material into the thin film resistor during operation of the integrated circuit, the hard mask material having been deposited using second collimated beams comprising the hard mask material and directed substantially perpendicular to the substrate surface;    a dielectric material overlaying the head mask material and defining a via formed in the dielectric material above a portion of the head mask material; and    a conductive material deposited in the via and coupled to the portion of the head mask material, the conductive material electrically connecting the thin film resistor to one or more other components of the integrated circuit.