Method for testing chips on flat solder bumps

Abstract

A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.

1 . A method for testing integrated circuit (IC) chips with probe needles on flat solder bumps comprising the steps of: 
 providing an IC chip with a multiplicity of bond pads on an active surface,    planting a multiplicity of solder bumps each having a height less than ½ of its diameter on said multiplicity of bond pads, and    contacting said solder bumps with probe needles and establishing electrical connections with a test circuit.    
     
     
         2 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the step of planting said multiplicity of solder bumps by a technique selected from the group consisting of evaporation, electroplating and molten solder screening.  
     
     
         3 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the step of planting said multiplicity of solder bumps each having a substantially flattened top surface.  
     
     
         4 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the steps of: 
 planting said multiplicity of solder bumps with a lead/tin solder material, and  
 planarizing said multiplicity of solder bumps forming a substantially flattened top surface on each of said bumps.  
 
     
     
         5 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the steps of: 
 planting said multiplicity of solder bumps with a solder material containing at least 80% lead, and  
 flatten the top surfaces of said multiplicity of solder bumps by a platen having a planar surface.  
 
     
     
         6 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the step of planting said multiplicity of solder bumps by a molten solder screening transfer process, each of said multiplicity of solder bumps having a flattened hemisphere.  
     
     
         7 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the step of planting said multiplicity of solder bumps by a molten solder screening technique in an in-situ mold such that each of the multiplicity of solder bumps planted has a flattened hemisphere.  
     
     
         8 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the steps of: 
 forming an in-situ solder mold on top of said IC chip with said multiplicity of solder bond pads exposed in a multiplicity of cavities,  
 filling said multiplicity of cavities with an electroplated solder material, and  
 removing said in-situ solder mold.  
 
     
     
         9 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 8 , wherein said in-situ solder mold is formed of a polymeric material.  
     
     
         10 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 8 , wherein said in-situ solder mold is formed of a screen-printable polyimide material.  
     
     
         11 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 8 , wherein said electroplated solder material filling said multiplicity of cavities forming short cylinders.  
     
     
         12 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 1  further comprising the steps of: 
 forming an in-situ solder mold on top of said IC chip with said multiplicity of bond pads exposed in a multiplicity of cavities,  
 filling said multiplicity of cavities with a solder material by a molten solder screening technique, and  
 leaving said in-situ solder mold in place.  
 
     
     
         13 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 12 , wherein said in-situ mold is formed of a screen-printable polyimide material.  
     
     
         14 . A method for testing IC chips with probe needles on flat solder bumps according to  claim 12  further comprising the step of reflowing said solder material into solder balls for a final chip attach process.  
     
     
         15 . An IC chip having substantially flattened solder bumps on an active surface comprising: 
 a multiplicity of bond pads formed on said active surface, and    a multiplicity of solder bumps formed in flattened hemi-spherical shape on said multiplicity of bond pads, each of said multiplicity of solder bumps having a height less than ½ of the maximum diameter of said hemi-spherical shapes.    
     
     
         16 . An IC chip having substantially flattened solder bumps on an active surface according to  claim 15 , wherein said multiplicity of solder bumps is formed of a lead-containing solder material.  
     
     
         17 . An IC chip having substantially flattened solder bumps on an active surface according to  claim 15 , wherein said multiplicity of solder bumps is formed of a soft solder material and flattened on the top surfaces by a flat platen.  
     
     
         18 . An IC chip having flat solder bumps on an active surface comprising: 
 a multiplicity of bond pads formed on said active surface, and    a multiplicity of solder bumps formed in cylindrical shape on said multiplicity of bond pads, each of said multiplicity of solder bumps having a height less than {fraction (1)} of the diameter of said cylindrical shape.    
     
     
         19 . An IC chip having flat solder bumps on an active surface according to  claim 18 , wherein said multiplicity of solder bumps is formed of a lead-containing solder material.  
     
     
         20 . An IC chip having flat solder bumps on an active surface according to  claim 18 , wherein said multiplicity of solder bumps is formed in a pancake shape.