[mask rom structure and manufacturing method thereof]

Abstract

A mask read-only-memory structure and its method of manufacture are provided. The structure includes a substrate, a buried bit line in the substrate and a patterned stack layer covering a portion of the upper surface of the substrate. The stack layer includes a first dielectric layer, a stopping layer and a second dielectric layer. A gate oxide layer covers a portion of the upper surface of the substrate. A word line runs across the buried bit line to form a plurality of coding cells. The memory cells having a stack layer thereon are at a logic state “0” while the memory cells having a gate oxide layer thereon are at a logic state “1”.

1 . A mask read-only-memory (ROM) structure, comprising: 
 a substrate;    a buried bit line embedded inside the substrate;    a patterned stack layer covering a portion of the upper surface of the substrate, wherein the stack layer comprises a first dielectric layer, a stopping layer and a second dielectric layer;    a gate oxide layer covering a portion of the upper surface of the substrate; and    a word line crossing over the buried bit line to form a plurality of coding cells, wherein the coding cells having a stack layer thereon are at a first data state while the coding cells having a gate oxide layer thereon are at a second data state.    
     
     
         2 . The mask ROM of  claim 1 , wherein the stack layer includes a first silicon oxide layer, a silicon oxynitride layer and a second silicon oxide layer stacked on top of each other.  
     
     
         3 . The mask ROM of  claim 1 , wherein the stack layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked on top of each other.  
     
     
         4 . The mask ROM of  claim 1 , wherein the first dielectric layer has a thickness between about 200 Å to 800 Å.  
     
     
         5 . The mask ROM of  claim 1 , wherein the stopping layer has a thickness between about 20 Å to 80 Å.  
     
     
         6 . The mask ROM of  claim 1 , wherein the second dielectric layer has a thickness between about 200 Å to 800 Å.