Method of separating semiconductor dies from a wafer
Abstract
Methods are disclosed for manufacturing semiconductor device dies and for separating dies from a semiconductor wafer, wherein one or more channels are etched in the top of the wafer between individual die areas. Material is then removed from the bottom side of the wafer in order to separate the individual dies. Methods are also disclosed for removing material from the bottom side of the wafer dies, wherein a contoured surface is provided on the die bottom, such as through an etching process. In addition, methods are disclosed for removing material from the bottom side of a wafer, and for securing a semiconductor device to a surface. Semiconductor wafers and dies are also disclosed having contoured bottom surfaces.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of separating dies from a wafer with top and bottom sides and having a plurality of electrical circuits in corresponding die areas of the wafer, the method comprising:
etching channels in the wafer extending into the wafer from the top side toward the bottom side, wherein the channels are located between the die areas of the wafer; mounting a carrier tape onto the top side of the die areas of the wafer; and removing material from the bottom side of the wafer to expose the channels and separate the dies from one another.
2 . The method of claim 1 , wherein etching channels in the wafer comprises removing material from the top side of the wafer using a dry chemical etch process.
3 . The method of claim 2 , wherein removing material using a dry chemical etch process comprises removing material using a directional plasma etch to create channels having a width of about 15 μm, and a depth of about 130 μm or more and about 200 μm or less.
4 . The method of claim 1 , wherein etching the channels in the wafer comprises removing material from the top side of the wafer using a reactive ion etching process.
5 . The method of claim 4 , wherein etching the channels in the wafer comprises providing a channel having a width of about 15 μm, and a depth of about 130 μm or more and about 200 μm or less.
6 . The method of claim 4 , wherein removing material from the bottom side of the wafer comprises at least one of grinding and etching.
7 . The method of claim 6 , wherein removing material from the bottom side of the wafer comprises etching a contoured surface in the bottom side of the wafer.
8 . The method of claim 7 , wherein etching a contoured surface comprises selectively etching the bottom side of the wafer to create the contoured surface.
9 . The method of claim 8 , wherein selectively etching the bottom side of the wafer comprises:
applying a pattern to the bottom side of the wafer using an etch resistant material; and selectively etching the bottom side pattern using a plasma to create the contoured surface.
10 . The method of claim 9 , wherein applying a pattern to the bottom side of the wafer comprises jetting polymer droplets in a dot pattern on the bottom side of the wafer.
11 . The method of claim 10 , wherein the polymer droplets have an etch rate compatible with that of the wafer, and wherein selectively etching the bottom side pattern comprises performing a non-directional etch on the bottom side until the channels are exposed.
12 . The method of claim 1 , wherein removing material from the bottom side of the wafer comprises at least one of grinding and etching.
13 . The method of claim 12 , wherein removing material from the bottom side of the wafer comprises etching a contoured surface in the bottom side of the wafer.
14 . The method of claim 13 , wherein etching a contoured surface comprises selectively etching the bottom side of the wafer to create the contoured surface.
15 . The method of claim 14 , wherein selectively etching the bottom side of the wafer comprises:
applying a pattern to the bottom side of the wafer using an etch resistant material; and selectively etching the bottom side pattern using a plasma to create the contoured surface.
16 . The method of claim 15 , wherein applying a pattern to the bottom side of the wafer comprises jetting polymer droplets in a dot pattern on the bottom side of the wafer.
17 . The method of claim 16 , wherein the polymer droplets have an etch rate compatible with that of the wafer, and wherein selectively etching the bottom side pattern comprises performing a non-directional etch on the bottom side until the channels are exposed.
18 . A method of fabricating semiconductor device dies, comprising:
providing a semiconductor wafer having top and bottom sides; creating at least one electrical circuit in a die area on the top side of the wafer; etching at least one channel in the top side of the wafer between the die area and the remainder of the wafer, wherein the at least one channel extends from the top side into the wafer toward the bottom side; and removing material from the bottom side of the wafer to expose the at least one channel in order to separate the die area from the remainder of the wafer.
19 . The method of claim 18 , wherein etching at least one channel in the top side of the wafer comprises removing material from the top side of the wafer using a reactive ion etch process.
20 . The method of claim 19 , wherein removing material from the bottom side of the wafer comprises at least one of grinding and etching.
21 . The method of claim 19 , wherein removing material from the bottom side of the wafer comprises plasma dry etching the bottom side of the wafer so as to remove material therefrom.
22 . The method of claim 21 , wherein removing material from the bottom side of the wafer comprises providing a contoured bottom surface on the bottom side of the wafer using a plasma etching process.
23 . The method of claim 18 , wherein removing material from the bottom side of the wafer comprises providing a contoured bottom surface on the bottom side of the wafer using a plasma etching process.
24 . A semiconductor wafer, comprising:
a plurality of die areas spaced from one another by a first distance; an electrical circuit located on a top side of the wafer within one of the die areas; and a plurality of channels extending from the top side into the wafer toward a bottom side of the wafer and separating the one of the die areas from the remainder of the die areas; wherein the first distance is about 90 μm or less.
25 . The wafer of claim 24 , wherein the first distance is about 50 μm or less and about 15 μm or more.
26 . The wafer of claim 25 , wherein the plurality of channels have a width of about 15 μm or less.
27 . The wafer of claim 26 , wherein the plurality of channels extend from the top side toward the bottom side by a second distance, and wherein the second distance is about 130 μm or more and about 200 μm or less.
28 . The wafer of claim 24 , wherein the plurality of channels have a width of about 15 μm or less, and wherein the plurality of channels extend from the top side toward the bottom side by a second distance of about 130 μm or more and about 200 μm or less.
29 . The wafer of claim 24 , wherein the electrical circuit comprises at least one stud bump on the top side operative for electrical connection with at least one of a circuit board and a suspension.Cited by (0)
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