Spacer like floating gate formation

Abstract

A split-gate flash memory cell having a spacer-like floating gate is disclosed as well as a method of forming the same. This is accomplished by defining a floating area opening in a structure layer over a substrate, and forming polysilicon spacers along the vertical walls of the opening. Then an intergate oxide is formed over the spacer-like floating gates followed by the forming of individual control gates. Thus, a flash memory is formed having two independent cells with their own spacer floating gates and control gates sharing one source with the capability of being shrunk in size much more readily than conventionally possible.

What is claimed is:  
     
         1 - 7 . (cancelled)  
     
     
         8 . A splitgate flash memory cell with a spacer-like floating gate comprising: 
 a substrate having active and field areas defined;    a source and drain regions in said active area;    floating spacers formed over and separated from said source region with a tunnel oxide;    an intergate oxide layer formed over said floating spacers; and    controlling layers formed over said intergate oxide layer sharing the same said source region.    
     
     
         9 . The split-gate flash memory cell of  claim 8 , wherein said substrate is silicon.  
     
     
         10 . The split-gate flash memory cell of  claim 8  wherein said floating spacers comprise a first polysilicon layer.  
     
     
         11 . The split-gate flash memory cell of  claim 8  wherein said floating spacers have a have a height and width between about 50 to 10000 A, and 50 to 10000 A, respectively.  
     
     
         12 . The split-gate flash memory cell of  claim 8  wherein said controlling layers comprise a second polysilicon layer to form control gates.  
     
     
         13 . The split-gate flash memory cell of  claim 8  wherein said controlling layer has a thickness between about 50 to 10000 A.