Implementation of Si-Ge HBT module with CMOS process

Abstract

A semiconductor device wherein Si-Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application and exposure to define where a HBT device will be placed. Plasma etching the Silicon dioxide layer to define an undercut, epitaxially growing an Si-Ge layer and a Silicon layer, and continuing manufacture to form one or more bipolar and CMOS devices and define interconnect and passivation.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a Silicon substrate;    Si-Ge on the Silicon substrate; and    Silicon on the Si-Ge, wherein the Si-Ge forms the base of a bipolar transistor and the Silicon on the Si-Ge forms the emitter of the bipolar transistor.    
     
     
         2 . A semiconductor device as defined in  claim 1 , wherein said semiconductor device includes a Silicon region which does not include any Si-Ge, and includes a Si-Ge region which includes Si-Ge on the Silicon substrate.  
     
     
         3 . A semiconductor device as defined in  claim 3 , wherein said Silicon region includes an oxide layer and said Si-Ge region does not include an oxide layer.  
     
     
         4 . A semiconductor device as defined in  claim 1 , wherein said semiconductor device includes a layer of Silicon dioxide on the Silicon substrate, said layer of Silicon dioxide having an exposed area in which the Si-Ge is disposed.  
     
     
         5 . A semiconductor device as defined in  claim 1 , wherein said semiconductor device includes a Silicon region which does not include any Si-Ge, and includes a Si-Ge region which includes Si-Ge on the Silicon substrate, further comprising a Silicon layer in said Si-Ge region, wherein the Si-Ge on the Silicon substrate forms a Si-Ge layer, said Silicon layer being disposed on the Si-Ge layer, said Si-Ge layer being disposed between said Silicon substrate and said Silicon layer in said Si-Ge region.  
     
     
         6 . A method of making a semiconductor device comprising: 
 providing a Silicon substrate;    depositing Si-Ge on the Silicon substrate;    depositing Silicon on the Si-Ge;    providing that said semiconductor device is configured such that the Si-Ge forms the base of a bipolar transistor and the Silicon on the Si-Ge forms the emitter of the bipolar transistor.    
     
     
         7 . A method as defined in  claim 6 , further comprising forming a Silicon dioxide layer on the Silicon substrate.  
     
     
         8 . A method as defined in  claim 7 , further comprising masking at least a portion of the oxide layer which is disposed on the Silicon substrate to define an implant well.  
     
     
         9 . A method as defined in  claim 8 , further comprising masking and implanting dopant to form a collector region of the bipolar transistor.  
     
     
         10 . A method as defined in  claim 9 , removing at least a portion of the Silicon dioxide layer which is disposed on the Silicon substrate in order to expose a portion of the Silicon substrate and create an undercut.  
     
     
         11 . A method as defined in  claim 10 , further comprising forming a Si-Ge layer on the exposed portion of the Silicon substrate.  
     
     
         12 . A method as defined in  claim 11 , further comprising forming a Silicon layer on the Si-Ge layer which is disposed on the Silicon substrate.  
     
     
         13 . A method as defined in  claim 10 , wherein the step of removing at least a portion of the Silicon dioxide layer comprises wet etching the portion of the Silicon dioxide layer.  
     
     
         14 . A method as defined in  claim 11 , wherein the step of forming a Si-Ge layer on the exposed portion of the Silicon substrate comprises epitaxially growing the Si-Ge layer.  
     
     
         15 . A method as defined in  claim 12 , wherein the step of forming a Silicon layer on the Si-Ge layer comprises epitaxially growing the Silicon layer.  
     
     
         16 . A method as defined in  claim 6 , further comprising masking and implanting dopant to define base and emitter regions of the bipolar transistor.