Method for producing semi-insulating resistivity in high purity silicon carbide crystals

Abstract

A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defect related deep level states to a temperature above the temperatures required for CVD growth of silicon carbide from source gases, but less than the sublimation temperature of silicon carbide under the ambient conditions to thereby thermodynamically increase the number of point defects and resulting states in the crystal, and then cooling the heated crystal to approach room temperature at a sufficiently rapid rate to maintain a concentration of point defects in the cooled crystal that remains greater than the first concentration.

That which is claimed is:  
     
         1 . A semi-insulating silicon carbide crystal made by the method of: 
 heating a silicon carbide crystal having a first concentration of point defect related deep level states to a temperature above the temperatures required for CVD growth of silicon carbide from source gases, but less than the sublimation temperature of silicon carbide under the ambient conditions to thereby thermodynamically increase the concentration of point defects and resulting states in the crystal; and    cooling the heated crystal to approach room temperature at a sufficiently rapid rate to maintain a concentration of point defects in the cooled crystal that remains greater than the first concentration.    
     
     
         2 . A compensated silicon carbide crystal according to  claim 1 .  
     
     
         3 . A compensated crystal according to  claim 2  in which the most concentrated dopant is present in an amount of about 5E16 or less.  
     
     
         4 . A semi-insulating silicon carbide crystal made by the method of: 
 heating a silicon carbide single crystal to a temperature of at least about 2000° C. to thereby thermodynamically increase the number of point defects and resulting deep level states in the crystal; and    cooling the heated crystal to approach room temperature at a sufficiently rapid rate to maintain a concentration of point defects in the cooled crystal that remains greater than the first concentration.    
     
     
         5 . A semi-insulating silicon carbide crystal according to  claim 4  having a polytype selected from the group consisting of the 3C, 4H, 6H, and 15R polytypes of silicon carbide.  
     
     
         6 . A wafer and epitaxial layer produced by the method of: 
 heating a silicon carbide substrate wafer to a temperature of at least about 2000° C.;    cooling the heated wafer to 1200° C. or less at a rate of at least about 30° C. per minute; and    depositing an epitaxial layer of a semiconductor material on the substrate wafer.    
     
     
         7 . A wafer and epitaxial layer thereon formed by the method of 
 heating a silicon carbide boule to a temperature of at least about 2000° C.;    cooling the heated boule to approach room temperature at a rate of at least about 30° C. per minute;    slicing a silicon carbide wafer from the boule; and    depositing an epitaxial layer of a semiconductor material on the sliced wafer.    
     
     
         8 . A device that incorporates the wafer and epitaxial layer according to  claim 7 .  
     
     
         9 . A device according to  claim 8  selected from the group consisting of FET's, MOSFET's, JFET's, MESFET's, HFET's, HEMT's, DMOS FET's, extended drain MOSFET's; vertical DMOS transistors, and lateral DMOS transistors.  
     
     
         10 . A wafer and epitaxial layer thereon formed by the method of 
 slicing a silicon carbide wafer from a single crystal silicon carbide boule;    heating the sliced wafer to a temperature of at least about 2000° C.;    cooling the heated wafer to approach room temperature at a rate of at least about 30° C. per minute; and    depositing an epitaxial layer of a semiconductor material on the sliced wafer.    
     
     
         11 . A device that incorporates the wafer and epitaxial layer according to  claim 10 .  
     
     
         12 . A device according to  claim 11  selected from the group consisting of FET's, MOSFET's, JFET's, MESFET's, HFET's, HEMT's, DMOS FET's, extended drain MOSFET's; vertical DMOS transistors, and lateral DMOS transistors.