Two-metal layer ball grid array and chip scale package having local interconnects used in wire-bonded and flip-chip semiconductor assembly

Abstract

The present invention comprises a low cost device ( 10, 20 ) and a method ( 30 ) of forming an electrical interconnect between two metal substrate layers configured in a flip-chip format or a wire bonded format. The invention includes a first metal substrate layer ( 12 ), a second metal substrate layer ( 14 ), and an organic tape layer ( 16 ) attached therebetween as a dielectric. The organic tape layer ( 16 ) includes a series of spaced apart vias ( 15 ) adapted to receive solder paste ( 13 ). The second metal layer ( 14 ) includes a plurality of openings ( 40,42,44 ) spaced along the surface thereof and coaxially aligned with the spaced vias ( 15 ). Further, the invention includes a plurality of solder balls ( 17, 18, 19 ) placed across the respective openings ( 40,42,44 ) of the second metal layer ( 14 ) such that each solder ball ( 17 - 19 ) attaches to the solder paste ( 13 ) forming an electrical interconnect running substantially in parallel between the metal layers ( 12, 14 ). The solder balls are adapted to communicate I/O signals or power to/from an IC supported on the first layer.

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         11 . A method of forming an electrical connection between first and second metal substrate layers of a semiconductor device package, comprising the steps of: 
 positioning a dielectric material between said first and second metal substrate layer;    forming a plurality of vias spaced apart at predetermined intervals within said dielectric material;    forming a plurality of openings at predetermined intervals along the surface of said second metal substrate layer such that said openings are aligned with said vias;    depositing solder paste within said vias; and    attaching a plurality of solder balls across said openings of said second metal layer, wherein said solder balls and said solder paste are solder-wetted to form an electrical interconnect.    
     
     
         12 . The method as specified in  claim 11  further comprising the step of attaching an integrated circuit to said first metal substrate layer in a flip-chip format.  
     
     
         13 . The method as specified in  claim 12  wherein one of said electrical interconnect balls are adapted to provide an input/output (I/O) signal function to said integrated circuit.  
     
     
         14 . The method as specified in  claim 12  wherein one of said electrical interconnect solder balls is adapted to provide a power function to said integrated circuit.  
     
     
         15 . The method as specified in  claim 12  wherein one of said electrical interconnect balls are adapted to provide a ground function to said integrated circuit.  
     
     
         16 . The method as specified in  claim 11  further comprising the step of attaching an integrated circuit to said first metal substrate layer and wire bonding said integrated circuit to said first metal substrate layer proximate said vias.  
     
     
         17 . The method as specified in  claim 11  wherein said dielectric material comprises an organic material.  
     
     
         18 . The method as specified in  claim 17  wherein said organic material comprises a polyimide tape, said polyimide tape having copper applied to both sides.  
     
     
         19 . The method as specified in  claim 11  wherein said first metal substrate layer is adapted to rate signals from said vias to said integrated circuit.  
     
     
         20 . The method as specified in  claim 11  wherein said solder balls and said solder paste are heat wetted to form an electrical interconnect substantially in parallel between said first and second layers.