Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate

Abstract

The present invention provides a method for manufacturing a semiconductor device comprising a III-V semiconductor substrate, and an insulating layer deposited on the substrate by Atomic Layer Deposition (ALD). The use of ALD to deposit the insulating layer was found to facilitate the creation of active devices that avoid Fermi layer pinning. In addition, such insulating layer may be advantageously used as a passivation layer in III-V substrate based active devices and transistors.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor device, comprising: 
 providing a III-V semiconductor substrate; and    depositing by Atomic Layer Deposition an insulating layer on said III-V semiconductor substrate.    
     
     
         2 . The method as recited in  claim 1 , further including performing a thermal anneal of said III-V semiconductor substrate before depositing said insulating layer.  
     
     
         3 . The method as recited in  claim 1 , further including forming an oxide layer on said III-V semiconductor substrate before depositing said insulating layer.  
     
     
         4 . The method as recited in  claim 1 , wherein said insulating layer is between about 0.5 and about 100 nm thick.  
     
     
         5 . The method as recited in  claim 1 , wherein said insulating layer is a first insulating layer and said method further comprises depositing a second insulating layer on said first insulating layer using a non-Atomic Layer Deposition process.  
     
     
         6 . The method as recited in  claim 1 , further comprising performing a second thermal anneal after depositing said insulating layer.  
     
     
         7 . The method as recited in  1 , wherein said semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET) and said method includes forming a gate, source and drain regions and a channel region between said source and drain regions, said MOSFET having a trap density of less than about 10 12  traps/cm 2 .  
     
     
         8 . The method as recited in  1 , wherein said MOSFET device has a transconductance of greater than about 2 mS/mm.  
     
     
         9 . An active device, comprising: 
 a III-V semiconductor substrate; and    an insulating layer deposited on said III-V semiconductor substrate by Atomic Layer Deposition.    
     
     
         10 . The device as recited in  claim 9 , wherein a surface of said III-V semiconductor substrate between said substrate and said insulating layer has a trap density of less than about 10 12  traps/cm 2 .  
     
     
         11 . The device as recited in  claim 9 , wherein said insulating layer has a dielectric constant of greater than about 8 and said insulating layer is selected from the group consisting of: 
 HfO 2 ;    ZrO 2 ;    Ta 2 O 5 ;    TiO 2 ;    Y 2 O 3 ;    La 2 O 3 ;    HfN; and    AlN.    
     
     
         12 . The device as recited in  claim 9 , wherein said insulating layer is Al 2 O 3 .  
     
     
         13 . The device as recited in  claim 9 , wherein said device is a metal oxide semiconductor field effect transistors (MOSFET) wherein said MOSFET includes a source and a drain region located in or on said III-V semiconductor substrate and said MOSFET is capable of operating when either a positive or a negative bias voltage is applied to said-gate.  
     
     
         14 . The device as recited in  claim 13 , wherein said positive bias voltage is up to about 30 V and said negative bias voltage is up to about −30 V.  
     
     
         15 . The device as recited in  claim 13 , wherein said MOSFET has a transconductance of greater than about 2 mS/mm.  
     
     
         16 . The device as recited in  claim 13 , wherein said MOSFET has a transconductance between about 100 and about 130 mS/mm.  
     
     
         17 . The device as recited in  claim 13 , wherein said MOSFET is an enhancement mode MOSFET or a depletion mode MOSFET.  
     
     
         18 . The device as recited in  claim 13 , further including said insulating layer between at least one of said source region and said gate, or said drain region and said gate, said insulating layer capable of acting as a passivation layer to hinder surface currents when a bias voltage is applied to said source, drain or gate.  
     
     
         19 . A transistor, comprising: 
 a III-V semiconductor substrate;    a gate located on said III-V semiconductor substrate;    a source and a drain formed in or on said III-V semiconductor substrate; and    an insulating layer deposited on said III-V semiconductor substrate by Atomic Layer Deposition between at least one of said source or drain region and said gate, said insulating layer capable of acting as a passivation layer to hinder surface currents when a bias voltage is applied to said source, drain or gate.    
     
     
         20 . The device as recited in  claim 19 , wherein said insulating layer is a first insulating layer and a second insulating layer is deposited on said first insulating layer, said second insulating layer deposited by a non-Atomic Layer Deposition process.