Memory chip having an integrated address scrambler unit and method for scrambling an address in an integrated memory

Abstract

A memory chip having an integrated address scrambler unit that has address inputs for applying an address and can be to scramble the address in various ways depending on control bits. In addition, a memory cell array is provided, which is connected downstream of the address scrambler unit. This allows an increase in flexibility during scrambling.

We claim:  
     
         1 . A memory chip, comprising: 
 an integrated address scrambler unit, the address scrambler unit having a plurality of address inputs for applying an address, the address scrambler unit designed to scramble the address depending on control bits; and    a memory cell array, the memory cell array beams connected downstream of the address scrambler unit.    
     
     
         2 . The memory chip as claimed in  claim 1 , wherein the address scrambler unit has a plurality of predefined scramblers, the predetermined scramblers designed such that the address can be scrambled differently depending on the control bits.  
     
     
         3 . The memory chip as claimed in  claim 2 , wherein one of the predefined scramblers has a first conversion element for converting a bit of the address and a first multiplexer for forwarding either the bit converted by the conversion or the unscrambled bit depending on one of the control bits.  
     
     
         4 . The memory chip as claimed in  claim 3 , wherein a second of the predefined scramblers has a second conversion element for converting an address bit of the address and a second multiplexer for forwarding either the address bit converted by the second conversion element or the address bit produced by one of the other predefined scramblers depending on one of the control bits.  
     
     
         5 . The memory chip as claimed in  claim 1 , wherein the address scrambler unit has a programmable scrambler, the programmable scrambler designed such that the address can be scrambled depending on the control bits.  
     
     
         6 . The memory chip as claimed in  claim 5 , wherein the programmable scrambler has a plurality of multiplexers whose input side is connected to a plurality of the address inputs, the programmable scrambler has a conversion unit which produces scrambled address bits from particular bits of the address and the bits supplied by the multiplexers, the control bits being used to control the multiplexers.  
     
     
         7 . The memory chip as claimed in  claim 3 , wherein the conversion element has an XOR gate whose input side is connected to a first address line and to a second address line.  
     
     
         8 . The memory chip as claimed in  claim 1 , wherein the control bits can be prescribed externally via a control connection.  
     
     
         9 . The memory chip as claimed in  claim 1 , wherein the address scrambler unit can be activated using an external signal.  
     
     
         10 . A method for scrambling an address in an integrated memory comprising: 
 a control command to prompt an address scrambler unit, the address scrambler unit being provided in the memory to select one scramble pattern from a plurality of scramble patterns for use in scrambling;    supplying the address to be scrambled is to the address scrambler unit;    scrambling the address using the address scrambler unit; and    supplying the scrambled address to a memory cell array provided in the memory.    
     
     
         11 . The method as claimed in  claim 10 , further comprising: testing the memory before scrambling the address.  
     
     
         12 . The memory chip as claimed in  claim 5 , wherein the conversion element has an XOR gate whose input side is connected to a first address line and to a second address line.