Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps

Abstract

A multi-level redistribution layer trace reduces current crowding in solder bumps of an integrated circuit package. A multi-level redistribution layer trace for an integrated circuit die includes a redistribution layer trace formed on the integrated circuit die in each of a plurality of electrically conductive layers and an I/O pad formed at a termination of the redistribution layer trace so that the I/O pad extends through each of the plurality of electrically conductive layers to form an electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers. The redistribution layer trace may also be slotted to divide current flow horizontally at the electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers.

1 . A multi-level redistribution layer trace for an integrated circuit die comprising: 
 a redistribution layer trace formed on the integrated circuit die in an electrically conductive layer of the integrated circuit die;    an I/O pad extending through the electrically conductive layer to form an electrical junction between the termination of the redistribution layer trace and the I/O pad; and    a slot formed in the redistribution layer trace to divide the current flow horizontally at the electrical junction.    
     
     
         2 . A method of making a multi-level redistribution layer trace of an integrated circuit die comprising steps for: 
 forming a redistribution layer trace in an electrically conductive layer of the integrated circuit die;    forming an I/O pad on the integrated circuit die that extends through the electrically conductive layer to form an electrical junction between the redistribution layer trace and the I/O pad; and    forming a slot in the redistribution layer trace that extends into the redistribution layer trace from the electrical junction between the redistribution layer trace and the I/O pad.