US2005026323A1PendingUtilityA1

Method of manufacturing a semiconductor device

Assignee: HITACHI LTDPriority: Nov 29, 1999Filed: Aug 25, 2004Published: Feb 3, 2005
Est. expiryNov 29, 2019(expired)· nominal 20-yr term from priority
H10W 72/5522H10W 74/00H10W 72/0198H10W 72/884H10W 90/754H10W 46/607H10W 46/601H10W 46/103H10W 72/07533H10W 72/07532H10W 90/734H10W 74/117H10W 74/016H10W 99/00H10W 74/014H10W 72/5525H10D 64/011
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Claims

Abstract

For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, here is disclosed a technique for finding out easily, even after the dicing process, the position of each resin-molded semiconductor device in its former state on the wiring substrate. It includes processing steps of implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.

Claims

exact text as granted — not AI-modified
1 - 15 . (Canceled)  
   
   
       16 . A method of manufacturing a semiconductor device comprising the steps of: 
 (a) providing a plurality of semiconductor chips and a wiring substrate, each of said semiconductor chips having a plurality of electrodes formed on a main surface thereof, said wiring substrate having a main surface, a plurality of electrodes formed thereon and a rear surface opposing said main surface, said wiring substrate having a substantially rectangular shape and having a plurality of chip mounting areas arranged in a matrix formation, said wiring substrate having a slit penetrating from said main surface to said rear surface and extending in a direction substantially parallel to a pair of shorter edges of said wiring substrate, said wiring substrate being divided by said slit to provide a first part and second part each having said plurality of chip mounting areas;    (b) mounting said plurality of semiconductor chips on said plurality of chip mounting areas of said first and second parts of said wiring substrate respectively;    (c) electrically connecting said plurality of electrodes of said semiconductor chip with said plurality of electrodes of said wiring substrate in each of said plurality of chip mounting areas;    (d) sealing said main surface of said wiring substrate and said plurality of semiconductor chips with a resin member by a transfer molding method to form a first resin block and a second resin block which are separated from each other on said wiring substrate, said first resin block sealing said plurality of chip mounting areas on said first part of said wiring substrate, said second resin block sealing said plurality of chip mounting areas on said second part of said wiring substrate; and    (e) after step (d), dividing said wiring substrate and said resin member including said first and second blocks, to provide a plurality of semiconductor packages each having said semiconductor chip sealed by a part of said resin member.    
   
   
       17 . A method of manufacturing a semiconductor device according to  claim 16 , wherein step (c) includes electrically connecting said plurality of electrodes of said semiconductor chips with said plurality of electrodes of said wiring substrate by a plurality of bonding wires, respectively.  
   
   
       18 . A method of manufacturing a semiconductor device according to  claim 16 , further comprising a step of forming a plurality of bump electrodes on said rear surface of said wiring substrate, prior to step (e), said plurality of bump electrodes functions as external connection terminals of said plurality of semiconductor packages.  
   
   
       19 . A method of manufacturing a semiconductor device according to  claim 16 , wherein said division of said wiring substrate and said resin member is performed by dicing in step (e).

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