Reconfigurable processing system and method

Abstract

A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.

1 . A processing system, comprising: 
 a plurality of configuration registers, each configuration register designed to store a configuration,    wherein an instruction selects one of the plurality of configuration registers based on a value in a configuration field of the instruction, and    wherein the instruction and the configuration stored in the selected configuration register are both executed.    
   
   
       2 . The system of  claim 1 , further comprising: 
 an instruction decode unit configured to determine the instruction controls; and    a configuration decode unit configured to determine controls of the configuration stored in the configuration register selected by the instruction.    
   
   
       3 . The system of  claim 2 , wherein an execution unit is controlled by the configuration controls in the absence of the instruction controls.  
   
   
       4 . The system of  claim 2 , the instruction further comprising a modification field configured to modify the configuration controls.  
   
   
       5 . The system of  claim 4 , further comprising a component to implement the modified configuration controls.  
   
   
       6 . The system of  claim 5 , wherein the component implementing the modified configuration controls comprises a multiplexer.  
   
   
       7 . The system of  claim 5 , wherein the component implementing the modified configuration controls comprises a logic circuit.  
   
   
       8 . The system of  claim 5 , wherein the component implementing the modified configuration controls comprises a function.  
   
   
       9 . The system of  claim 4 , wherein different configuration controls are decoded from a single configuration as a result of the modified configuration controls.  
   
   
       10 . The system of  claim 4 , wherein the modified configuration controls result in an altered operation code of an execution unit.  
   
   
       11 . The system of  claim 4 , wherein the modified configuration controls result in an altered register number.  
   
   
       12 . The system of  claim 4 , wherein the modified configuration controls result in an inhibited register write function.  
   
   
       13 . The system of  claim 4 , wherein the modified configuration controls result in a cleared register.  
   
   
       14 . The system of  claim 4 , wherein the modified configuration controls result in an incremented counter.  
   
   
       15 . The system of  claim 2 , further comprising a register configured to provide operands requested by the instruction and configuration controls.  
   
   
       16  The system of  claim 15 , wherein the register comprises a register file.  
   
   
       17 . The system of  claim 15 , further comprising an execution unit configured to process the operands from the register according to the instruction and configuration controls.  
   
   
       18 . The system of  claim 17 , wherein the execution unit comprises an arithmetic logic unit  
   
   
       19 . The system of  claim 17 , wherein the execution unit comprises a shift unit.  
   
   
       20 . The system of  claim 17 , wherein the execution unit comprises a multiply unit.  
   
   
       21 . The system of  claim 17 , wherein the execution unit is configured to generate a result.  
   
   
       22 . The system of  claim 21 , wherein the result is stored to an internal register.  
   
   
       23 . The system of  claim 21 , wherein the result is stored to a register file.  
   
   
       24 . The system of  claim 21 , wherein the result is stored to a predicate register.  
   
   
       25 . The system of  claim 21 , wherein the result is stored to a memory.  
   
   
       26 . The system of  claim 21 , wherein the result is provided to an execution unit.  
   
   
       27 . The system of  claim 1 , wherein a plurality of configurations are loaded from a memory to respective configuration registers with a load instruction, the load instruction comprising: 
 one or more operation code fields that control loading of the configurations;    a configuration field identifying a configuration register that is loaded from the memory; and    a displacement indicating a memory address storing a configuration to be loaded into the configuration register.    
   
   
       28 . The system of  claim 27 , wherein a path to fetch the instruction that selects one of the plurality of configuration registers is also used to load the configuration into the configuration register.  
   
   
       29 . The system of  claim 27 , wherein the configuration registers are loaded while previously loaded configurations are executed.  
   
   
       30 . The system of  claim 1 , wherein the instruction and configuration controls execute an operation on scalar data.  
   
   
       31 . The system of  claim 1 , wherein the instruction and configuration controls execute an operation on vector data.  
   
   
       32 . The system of  claim 1 , wherein the instruction and configuration controls execute an operation on vector and scalar data.  
   
   
       33 . A vector processing system, comprising: 
 a plurality of configuration registers, each configuration register configured to store a configuration, 
 wherein an instruction selects one of the plurality of configuration registers based on a value in a configuration field of the instruction, and  
 wherein the instruction and the configuration stored in the selected configuration register are both executed;  
   a vector register file configured with one or more write and read ports to store one or more vectors, each vector including a plurality of vector elements; and    a vector address unit configured to provide an address of a vector element to be processed by the instruction and the configuration to the vector register file.    
   
   
       34 . The system of  claim 33 , wherein a vector element in an address identified by the vector address unit is provided through a read port of the vector register file and processed according to the instruction and configuration controls.  
   
   
       35 . The system of  claim 33 , wherein a vector element is provided through a write port and stored to an address of the vector register file identified by the vector address unit according to the instruction and configuration controls.  
   
   
       36 . The system of  claim 33 , each of the vector address units further comprising: 
 a register configured to store a current address of an element of the vector; and    an adder configured to add a stride to the current address,    wherein, for each vector element, the current address is incremented by the stride to identify an address of the next vector element to be processed.    
   
   
       37 . The system of  claim 36 , wherein the stride comprises an implicit stride.  
   
   
       38 . The system of  claim 36 , further comprising a stride register, wherein the stride comprises an address stride provided by the stride register.  
   
   
       39 . The system of  claim 36 , further comprising a multiplexer configured to select an address of a vector element provided to the vector register file.  
   
   
       40 . The system of  claim 39 , wherein the vector element address is the current address.  
   
   
       41 . The system of  claim 39 , wherein the vector element address is provided by an immediate value of the instruction.  
   
   
       42 . The system of  claim 39 , wherein the vector element address is an address from another register.  
   
   
       43 . The system of  claim 36 , the vector address unit further comprising a register configured to store a start address of the vector.  
   
   
       44 . The system of  claim 36 , the vector address unit further comprising a register configured to store a frame stride that increments the start address with the adder after all of the elements of a first vector have been processed, the incremented start address identifying the start address of a second vector.  
   
   
       45 . The system of  claim 36 , further comprising: 
 a vector length register; and    a vector count register, wherein 
 the vector length register is configured to store a value representing a number of elements in the vector,  
 an initial value of the vector count register is the value of the vector length register, and  
 the vector count register is decremented beginning from the value in the vector length register for each vector element processed.  
   
   
   
       46 . The system of  claim 36 , wherein a finite impulse response filter is implemented by processing vector data based on controls from the instruction and the configuration.  
   
   
       47 . The system of  claim 36 , wherein a finite impulse response filter is implemented by processing vector and scalar data based on controls from the instruction and the configuration.